axi_ad9963: Integrated ADC/DAC clock enables
Adrian Costina
Lars-Peter Clausen
parent
118dd18ba0
commit
d43ba5d26e
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@ -154,6 +154,8 @@ module axi_ad9963 #(
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wire up_rack_rx_s;
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wire [31:0] up_rdata_tx_s;
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wire up_rack_tx_s;
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wire up_adc_ce;
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wire up_dac_ce;
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// signal name changes
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@ -188,8 +190,10 @@ module axi_ad9963 #(
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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.up_adc_ce(up_adc_ce),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.up_dac_ce(up_dac_ce),
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.up_clk (up_clk),
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.up_adc_dld (up_adc_dld_s),
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.up_adc_dwdata (up_adc_dwdata_s),
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@ -210,6 +214,7 @@ module axi_ad9963 #(
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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.up_adc_ce(up_adc_ce),
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.up_dld (up_adc_dld_s),
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.up_dwdata (up_adc_dwdata_s),
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.up_drdata (up_adc_drdata_s),
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@ -256,6 +261,7 @@ module axi_ad9963 #(
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.dac_data_q (dac_data_q),
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.dac_dovf(dac_dovf),
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.dac_dunf(dac_dunf),
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.up_dac_ce(up_dac_ce),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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@ -0,0 +1 @@
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set_false_path -from [get_cells -hier -filter {name =~ *up_*ce_reg* && IS_SEQUENTIAL}] -to [get_pins -hier -filter {name =~ *bufgctrl*/S0}]
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@ -24,9 +24,6 @@
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// This interface includes both the transmit and receive components -
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// They both uses the same clock (sourced from the receiving side).
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// assumes RX_IQ is 1 for I and 0 for Q (RX_IFIRST = 1 , RXIQ_HILO = 1)
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`timescale 1ns/100ps
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@ -62,11 +59,13 @@ module axi_ad9963_if #(
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output reg adc_valid,
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output reg [23:0] adc_data,
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output reg adc_status,
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input up_adc_ce,
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// transmit data path interface
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input dac_valid,
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input [23:0] dac_data,
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input up_dac_ce,
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// delay interface
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@ -101,7 +100,7 @@ module axi_ad9963_if #(
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adc_valid <= 1'b1; // data[23:12] Q
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end else begin
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rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge
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adc_data <= {rx_data_p, rx_data_n_s} ; // so we take current N data with previous P data
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adc_data <= {rx_data_p, rx_data_n_s}; // so we take current N data with previous P data
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adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA
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end
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end
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@ -123,9 +122,22 @@ module axi_ad9963_if #(
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// device clock interface (receive clock)
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BUFG i_clk_gbuf (
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.I (trx_clk),
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.O (adc_clk));
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BUFGCTRL #(
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.INIT_OUT(0),
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.PRESELECT_I0("FALSE"),
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.PRESELECT_I1("FALSE")
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)
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bufgctrl_adc (
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.O(adc_clk),
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.CE0(1'b1),
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.CE1(1'b0),
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.I0(trx_clk),
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.I1(1'b0),
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.IGNORE0(1'b0),
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.IGNORE1(1'b0),
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.S0(up_adc_ce),
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.S1(1'b0)
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);
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// receive data interface, ibuf -> idelay -> iddr
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@ -183,9 +195,22 @@ module axi_ad9963_if #(
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.I (tx_clk),
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.O (div_clk));
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BUFG dac_bufg (
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.I(div_clk),
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.O(dac_clk));
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BUFGCTRL #(
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.INIT_OUT(0),
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.PRESELECT_I0("FALSE"),
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.PRESELECT_I1("FALSE")
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)
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bufgctrl_dac (
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.O(dac_clk),
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.CE0(1'b1),
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.CE1(1'b0),
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.I0(div_clk),
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.I1(1'b0),
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.IGNORE0(1'b0),
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.IGNORE1(1'b0),
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.S0(up_dac_ce),
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.S1(1'b0)
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);
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generate
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for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
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@ -28,6 +28,7 @@ adi_ip_files axi_ad9963 [list \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_dac_common.v" \
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"$ad_hdl_dir/library/common/up_dac_channel.v" \
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"axi_ad9963_constr.xdc" \
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"axi_ad9963_if.v" \
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"axi_ad9963_rx_pnmon.v" \
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"axi_ad9963_rx_channel.v" \
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@ -44,7 +45,6 @@ set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_cor
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ipx::remove_bus_interface rst [ipx::current_core]
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ipx::remove_bus_interface clk [ipx::current_core]
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ipx::remove_bus_interface l_clk [ipx::current_core]
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ipx::remove_bus_interface delay_clk [ipx::current_core]
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ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
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@ -73,6 +73,8 @@ module axi_ad9963_rx #(
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input adc_dovf,
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input adc_dunf,
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output up_adc_ce,
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// processor interface
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input up_rstn,
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@ -221,6 +223,7 @@ module axi_ad9963_rx #(
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.adc_usr_chanmax (8'd1),
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.up_adc_gpio_in (32'h0),
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.up_adc_gpio_out (),
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.up_adc_ce(up_adc_ce),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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@ -68,6 +68,8 @@ module axi_ad9963_tx #(
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input dac_dovf,
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input dac_dunf,
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output up_dac_ce,
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// processor interface
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input up_rstn,
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@ -81,16 +83,10 @@ module axi_ad9963_tx #(
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output reg [31:0] up_rdata,
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output reg up_rack);
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// internal registers
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reg dac_data_sync = 'd0;
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reg [ 7:0] dac_rate_cnt = 'd0;
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// internal signals
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wire dac_data_sync_s;
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wire dac_dds_format_s;
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wire [ 7:0] dac_datarate_s;
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wire [23:0] dac_data_int_s;
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wire [31:0] up_rdata_s[0:2];
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wire up_rack_s[0:2];
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@ -100,27 +96,19 @@ module axi_ad9963_tx #(
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assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
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always @(posedge dac_clk) begin
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dac_data_sync <= dac_data_sync_s;
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end
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// rate counters and data sync signals
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always @(posedge dac_clk) begin
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if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 8'd0)) begin
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dac_rate_cnt <= dac_datarate_s;
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end else begin
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dac_rate_cnt <= dac_rate_cnt - 1'b1;
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end
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end
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// dma interface
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always @(posedge dac_clk) begin
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dac_valid <= (dac_rate_cnt == 8'd0) ? 1'b1 : 1'b0;
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if (dac_rst == 1'b1) begin
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dac_valid <= 1'b0;
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dac_valid_i <= 1'b0;
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dac_valid_q <= 1'b0;
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end else begin
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dac_valid <= 1'b1;
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dac_valid_i <= dac_valid;
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dac_valid_q <= dac_valid;
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end
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end
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// processor read interface
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@ -146,7 +134,7 @@ module axi_ad9963_tx #(
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.dac_data_out (dac_data_int_s[11:0]),
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.dac_data_in (dac_data_int_s[23:12]),
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.dac_enable (dac_enable_i),
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.dac_data_sync (dac_data_sync),
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.dac_data_sync (dac_data_sync_s),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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@ -175,7 +163,7 @@ module axi_ad9963_tx #(
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.dac_data_out (dac_data_int_s[23:12]),
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.dac_data_in (dac_data_int_s[11:0]),
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.dac_enable (dac_enable_q),
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.dac_data_sync (dac_data_sync),
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.dac_data_sync (dac_data_sync_s),
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.dac_dds_format (dac_dds_format_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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@ -206,11 +194,12 @@ module axi_ad9963_tx #(
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.dac_par_enb (),
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.dac_r1_mode (),
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.dac_datafmt (dac_dds_format_s),
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.dac_datarate (dac_datarate_s),
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.dac_datarate (),
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.dac_status (1'b1),
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.dac_status_ovf (dac_dovf),
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.dac_status_unf (dac_dunf),
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.dac_clk_ratio (32'd1),
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.up_dac_ce(up_dac_ce),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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