library- remove ad_cmos_*
Rejeesh Kutty
parent
c15db8b74e
commit
d4820dd55a
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@ -1,82 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_cmos_clk #(
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parameter DEVICE_TYPE = 0) (
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input rst,
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output locked,
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input clk_in,
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output clk);
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localparam SERIES7 = 0;
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localparam VIRTEX6 = 1;
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// wires
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wire clk_ibuf_s;
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// defaults
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assign locked = 1'b1;
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// instantiations
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IBUFG i_rx_clk_ibuf (
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.I (clk_in),
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.O (clk_ibuf_s));
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generate
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if (DEVICE_TYPE == VIRTEX6) begin
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BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_rbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (clk_ibuf_s),
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.O (clk));
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end else begin
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BUFG i_clk_gbuf (
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.I (clk_ibuf_s),
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.O (clk));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -1,170 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_cmos_in #(
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parameter DEVICE_TYPE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// data interface
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input rx_clk,
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input rx_data_in,
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output rx_data_p,
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output reg rx_data_n,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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localparam SERIES7 = 0;
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localparam VIRTEX6 = 1;
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// internal registers
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// internal signals
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wire rx_data_n_s;
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wire rx_data_ibuf_s;
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wire rx_data_idelay_s;
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// delay controller
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generate
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if (IODELAY_CTRL == 1) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end else begin
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assign delay_locked = 1'b1;
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end
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endgenerate
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// receive data interface, ibuf -> idelay -> iddr
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IBUF i_rx_data_ibuf (
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.I (rx_data_in),
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.O (rx_data_ibuf_s));
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generate
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if (DEVICE_TYPE == VIRTEX6) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IODELAYE1 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("I"),
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.HIGH_PERFORMANCE_MODE ("TRUE"),
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.IDELAY_TYPE ("VAR_LOADABLE"),
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.IDELAY_VALUE (0),
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.ODELAY_TYPE ("FIXED"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.SIGNAL_PATTERN ("DATA"))
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i_rx_data_idelay (
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.T (1'b1),
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.CE (1'b0),
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.INC (1'b0),
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.CLKIN (1'b0),
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.DATAIN (1'b0),
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.ODATAIN (1'b0),
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.CINVCTRL (1'b0),
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.C (up_clk),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.RST (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end else begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_rx_data_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.IDATAIN (rx_data_ibuf_s),
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.DATAOUT (rx_data_idelay_s),
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.LD (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end
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endgenerate
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IDDR #(
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.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.SRTYPE ("ASYNC"))
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i_rx_data_iddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (rx_clk),
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.D (rx_data_idelay_s),
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.Q1 (rx_data_p),
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.Q2 (rx_data_n_s));
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always @(posedge rx_clk) begin
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rx_data_n <= rx_data_n_s;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -1,140 +0,0 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
|
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// terms.
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//
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// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
|
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// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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||||
// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_cmos_out #(
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parameter DEVICE_TYPE = 0,
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parameter IODELAY_ENABLE = 0,
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parameter IODELAY_CTRL = 0,
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parameter IODELAY_GROUP = "dev_if_delay_group") (
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// data interface
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input tx_clk,
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input tx_data_p,
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input tx_data_n,
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output tx_data_out,
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// delay-data interface
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input up_clk,
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input up_dld,
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input [ 4:0] up_dwdata,
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output [ 4:0] up_drdata,
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// delay-cntrl interface
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input delay_clk,
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input delay_rst,
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output delay_locked);
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localparam SERIES7 = 0;
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localparam VIRTEX6 = 1;
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// internal signals
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wire tx_data_oddr_s;
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wire tx_data_odelay_s;
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// delay controller
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generate
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if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7) && (IODELAY_CTRL == 1)) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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IDELAYCTRL i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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end else begin
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assign delay_locked = 1'b1;
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end
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endgenerate
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// transmit data interface, oddr -> odelay -> obuf
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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i_tx_data_oddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (tx_clk),
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.D1 (tx_data_p),
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.D2 (tx_data_n),
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.Q (tx_data_oddr_s));
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generate
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if ((IODELAY_ENABLE == 1) && (DEVICE_TYPE == SERIES7)) begin
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(* IODELAY_GROUP = IODELAY_GROUP *)
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ODELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("ODATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.ODELAY_TYPE ("VAR_LOAD"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_tx_data_odelay (
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.CE (1'b0),
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.CLKIN (1'b0),
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.INC (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (up_clk),
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.ODATAIN (tx_data_oddr_s),
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.DATAOUT (tx_data_odelay_s),
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.LD (up_dld),
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.CNTVALUEIN (up_dwdata),
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.CNTVALUEOUT (up_drdata));
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end else begin
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assign up_drdata = 5'd0;
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assign tx_data_odelay_s = tx_data_oddr_s;
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end
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endgenerate
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OBUF i_tx_data_obuf (
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.I (tx_data_odelay_s),
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.O (tx_data_out));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -16,7 +16,7 @@ M_DEPS += ../../scripts/adi_board.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/xilinx/common/ad_cmos_clk.v
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M_DEPS += ../../../library/xilinx/common/ad_data_clk.v
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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