zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad9081_fmca_ebz/vck190: Expose ref clock parameter

main
Laszlo Nagy 2022-08-03 11:01:58 +01:00 committed by Laszlo Nagy
parent 78333b2c90
commit d48b1bcdce
2 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
View File

@ -143,7 +143,11 @@ if {$ADI_PHY_SEL == 1} {
} else {
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
create_versal_phy jesd204_phy $TX_NUM_OF_LANES
set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \
? $ad_project_params(REF_CLK_RATE) : 360 } ]
# TODO:
# Assumption is that number of Tx and Rx lane is the same
create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE
}

2
projects/ad9081_fmca_ebz/vck190/system_project.tcl
View File

@ -20,6 +20,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
#
# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
# [RX/TX]_JESD_M : Number of converters per link
# [RX/TX]_JESD_L : Number of lanes per link
# [RX/TX]_JESD_S : Number of samples per frame
@ -34,6 +35,7 @@ adi_project ad9081_fmca_ebz_vck190 0 [list \
JESD_MODE [get_env_param JESD_MODE 64B66B ]\
RX_LANE_RATE [get_env_param RX_RATE 11.88 ] \
TX_LANE_RATE [get_env_param TX_RATE 11.88 ] \
REF_CLK_RATE [get_env_param REF_CLK_RATE 360 ] \
RX_JESD_M [get_env_param RX_JESD_M 2 ] \
RX_JESD_L [get_env_param RX_JESD_L 2 ] \
RX_JESD_S [get_env_param RX_JESD_S 4 ] \