ad9081_fmca_ebz/vck190: Expose ref clock parameter
parent
78333b2c90
commit
d48b1bcdce
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@ -143,7 +143,11 @@ if {$ADI_PHY_SEL == 1} {
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} else {
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} else {
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
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create_versal_phy jesd204_phy $TX_NUM_OF_LANES
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set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \
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? $ad_project_params(REF_CLK_RATE) : 360 } ]
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# TODO:
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# Assumption is that number of Tx and Rx lane is the same
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create_versal_phy jesd204_phy $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE
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}
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}
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@ -20,6 +20,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
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#
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#
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# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
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# RX_RATE : Line rate of the Rx link ( MxFE to FPGA )
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# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
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# TX_RATE : Line rate of the Tx link ( FPGA to MxFE )
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# REF_CLK_RATE : Frequency of reference clock in MHz used in 64B66B mode
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_S : Number of samples per frame
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# [RX/TX]_JESD_S : Number of samples per frame
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@ -34,6 +35,7 @@ adi_project ad9081_fmca_ebz_vck190 0 [list \
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JESD_MODE [get_env_param JESD_MODE 64B66B ]\
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JESD_MODE [get_env_param JESD_MODE 64B66B ]\
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RX_LANE_RATE [get_env_param RX_RATE 11.88 ] \
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RX_LANE_RATE [get_env_param RX_RATE 11.88 ] \
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TX_LANE_RATE [get_env_param TX_RATE 11.88 ] \
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TX_LANE_RATE [get_env_param TX_RATE 11.88 ] \
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REF_CLK_RATE [get_env_param REF_CLK_RATE 360 ] \
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RX_JESD_M [get_env_param RX_JESD_M 2 ] \
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RX_JESD_M [get_env_param RX_JESD_M 2 ] \
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RX_JESD_L [get_env_param RX_JESD_L 2 ] \
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RX_JESD_L [get_env_param RX_JESD_L 2 ] \
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RX_JESD_S [get_env_param RX_JESD_S 4 ] \
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RX_JESD_S [get_env_param RX_JESD_S 4 ] \
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