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library: register map changes and for mathworks

main
Rejeesh Kutty 2014-06-24 14:23:56 -04:00
parent e650253013
commit d4be46cc17
12 changed files with 622 additions and 289 deletions
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10
library/common/ad_dcfilter.v
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@ -78,6 +78,7 @@ module ad_dcfilter (
reg [15:0] data_d = 'd0; reg [15:0] data_d = 'd0;
reg valid_2d = 'd0; reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0; reg [15:0] data_2d = 'd0;
reg [15:0] data_dcfilt = 'd0;
reg valid_out = 'd0; reg valid_out = 'd0;
reg [15:0] data_out = 'd0; reg [15:0] data_out = 'd0;
@ -96,13 +97,14 @@ module ad_dcfilter (
data_d <= data + dcfilt_offset; data_d <= data + dcfilt_offset;
end end
valid_2d <= valid_d; valid_2d <= valid_d;
data_2d <= data_d - dc_offset; data_2d <= data_d;
data_dcfilt <= data_d - dc_offset;
if (dcfilt_enb == 1'b1) begin if (dcfilt_enb == 1'b1) begin
valid_out <= valid_2d; valid_out <= valid_2d;
data_out <= data_2d; data_out <= data_dcfilt;
end else begin end else begin
valid_out <= valid_d; valid_out <= valid_2d;
data_out <= data_d; data_out <= data_2d;
end end
end end

12
library/common/ad_dds.v
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@ -45,7 +45,6 @@ module ad_dds (
clk, clk,
dds_format, dds_format,
dds_enable,
dds_phase_0, dds_phase_0,
dds_scale_0, dds_scale_0,
dds_phase_1, dds_phase_1,
@ -56,7 +55,6 @@ module ad_dds (
input clk; input clk;
input dds_format; input dds_format;
input dds_enable;
input [15:0] dds_phase_0; input [15:0] dds_phase_0;
input [15:0] dds_scale_0; input [15:0] dds_scale_0;
input [15:0] dds_phase_1; input [15:0] dds_phase_1;
@ -70,21 +68,15 @@ module ad_dds (
// internal signals // internal signals
wire [15:0] dds_data_int_s;
wire [15:0] dds_data_0_s; wire [15:0] dds_data_0_s;
wire [15:0] dds_data_1_s; wire [15:0] dds_data_1_s;
// dds channel output // dds channel output
assign dds_data_int_s = {(dds_format ^ dds_data_int[15]), dds_data_int[14:0]};
always @(posedge clk) begin always @(posedge clk) begin
dds_data_int <= dds_data_0_s + dds_data_1_s; dds_data_int <= dds_data_0_s + dds_data_1_s;
if (dds_enable == 1'b1) begin dds_data[15:15] <= dds_data_int[15] ^ dds_format;
dds_data <= dds_data_int_s; dds_data[14: 0] <= dds_data_int[14:0];
end else begin
dds_data <= 16'd0;
end
end end
// dds-1 // dds-1

217
library/common/ad_dds_sine.v
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@ -66,127 +66,150 @@ module ad_dds_sine (
// internal registers // internal registers
reg [DW:0] ddata_s2_i = 'd0; reg [ 33:0] s1_data_p = 'd0;
reg data_msb_s2_i = 'd0; reg [ 33:0] s1_data_n = 'd0;
reg [15:0] data_delay_s2_i = 'd0; reg [ 15:0] s1_angle = 'd0;
reg [15:0] data_sine_s2_i = 'd0; reg [ DW:0] s1_ddata = 'd0;
reg [DW:0] ddata_s2 = 'd0; reg [ 18:0] s2_data_0 = 'd0;
reg data_msb_s2 = 'd0; reg [ 18:0] s2_data_1 = 'd0;
reg [15:0] data_sine_s2 = 'd0; reg [ DW:0] s2_ddata = 'd0;
reg [DW:0] ddata_s3_i = 'd0; reg [ 18:0] s3_data = 'd0;
reg data_msb_s3_i = 'd0; reg [ DW:0] s3_ddata = 'd0;
reg [15:0] data_delay_s3_i = 'd0; reg [ 33:0] s4_data2_p = 'd0;
reg [15:0] data_sine_s3_i = 'd0; reg [ 33:0] s4_data2_n = 'd0;
reg [DW:0] ddata_s4 = 'd0; reg [ 16:0] s4_data1_p = 'd0;
reg data_msb = 'd0; reg [ 16:0] s4_data1_n = 'd0;
reg [14:0] data_sine_p = 'd0; reg [ DW:0] s4_ddata = 'd0;
reg [14:0] data_sine_n = 'd0; reg [ 16:0] s5_data2_0 = 'd0;
reg [DW:0] ddata_out = 'd0; reg [ 16:0] s5_data2_1 = 'd0;
reg [ 16:0] s5_data1 = 'd0;
reg [ DW:0] s5_ddata = 'd0;
reg [ 16:0] s6_data2 = 'd0;
reg [ 16:0] s6_data1 = 'd0;
reg [ DW:0] s6_ddata = 'd0;
reg [ 33:0] s7_data = 'd0;
reg [ DW:0] s7_ddata = 'd0;
reg [ 15:0] sine = 'd0; reg [ 15:0] sine = 'd0;
reg [ DW:0] ddata_out = 'd0;
// internal signals // internal signals
wire [DW:0] ddata_s1_s; wire [ 15:0] angle_s;
wire data_msb_s1_s; wire [ 33:0] s1_data_s;
wire [31:0] data_sine_s1_s; wire [ DW:0] s1_ddata_s;
wire [DW:0] ddata_s2_i_s; wire [ 15:0] s1_angle_s;
wire data_msb_s2_i_s; wire [ 33:0] s4_data2_s;
wire [15:0] data_delay_s2_i_s; wire [ DW:0] s4_ddata_s;
wire [31:0] data_sine_s2_i_s; wire [ 16:0] s4_data1_s;
wire [DW:0] ddata_s2_s; wire [ 33:0] s7_data2_s;
wire data_msb_s2_s; wire [ 33:0] s7_data1_s;
wire [31:0] data_sine_s2_s; wire [ DW:0] s7_ddata_s;
wire [DW:0] ddata_s3_i_s;
wire data_msb_s3_i_s;
wire [15:0] data_delay_s3_i_s;
wire [31:0] data_sine_s3_i_s;
wire [DW:0] ddata_s3_s;
wire data_msb_s3_s;
wire [31:0] data_sine_s3_s;
// level 1 (intermediate) A*x; // make angle 2's complement
ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s1 ( assign angle_s = {~angle[15], angle[14:0]};
// level 1 - intermediate
ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+16)) i_mul_s1 (
.clk (clk), .clk (clk),
.data_a ({1'b0, angle[14:0]}), .data_a ({angle_s[15], angle_s}),
.data_b (16'hc90f), .data_b ({angle_s[15], angle_s}),
.data_p (data_sine_s1_s), .data_p (s1_data_s),
.ddata_in ({ddata_in, angle[15]}), .ddata_in ({ddata_in, angle_s}),
.ddata_out ({ddata_s1_s, data_msb_s1_s})); .ddata_out ({s1_ddata_s, s1_angle_s}));
// level 1, (final) B*x; // 2's complement versions
ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2_i (
.clk (clk),
.data_a (data_sine_s1_s[30:15]),
.data_b (16'h19f0),
.data_p (data_sine_s2_i_s),
.ddata_in ({ddata_s1_s, data_msb_s1_s, data_sine_s1_s[30:15]}),
.ddata_out ({ddata_s2_i_s, data_msb_s2_i_s, data_delay_s2_i_s}));
// level 2 inputs, B*x and (1-A*x)
always @(posedge clk) begin always @(posedge clk) begin
ddata_s2_i <= ddata_s2_i_s; s1_data_p <= s1_data_s;
data_msb_s2_i <= data_msb_s2_i_s; s1_data_n <= ~s1_data_s + 1'b1;
data_delay_s2_i <= data_delay_s2_i_s; s1_angle <= s1_angle_s;
data_sine_s2_i <= 16'ha2f9 - data_sine_s2_i_s[28:13]; s1_ddata <= s1_ddata_s;
end end
// level 2, second order (A*x2 + B*x) // select partial products
ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s2 (
.clk (clk),
.data_a (data_delay_s2_i),
.data_b (data_sine_s2_i),
.data_p (data_sine_s2_s),
.ddata_in ({ddata_s2_i, data_msb_s2_i}),
.ddata_out ({ddata_s2_s, data_msb_s2_s}));
always @(posedge clk) begin always @(posedge clk) begin
ddata_s2 <= ddata_s2_s; s2_data_0 <= (s1_angle[15] == 1'b0) ? s1_data_n[31:13] : s1_data_p[31:13];
data_msb_s2 <= data_msb_s2_s; s2_data_1 <= {s1_angle[15], s1_angle[15:0], 2'b00};
if (data_sine_s2_s[31:29] == 0) begin s2_ddata <= s1_ddata;
data_sine_s2 <= data_sine_s2_s[28:13];
end else begin
data_sine_s2 <= 16'hffff;
end
end end
// level 2, intermediate (B*y) // unit-sine
ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s3_i (
.clk (clk),
.data_a (data_sine_s2),
.data_b (16'h3999),
.data_p (data_sine_s3_i_s),
.ddata_in ({ddata_s2, data_msb_s2, data_sine_s2}),
.ddata_out ({ddata_s3_i_s, data_msb_s3_i_s, data_delay_s3_i_s}));
always @(posedge clk) begin always @(posedge clk) begin
ddata_s3_i <= ddata_s3_i_s; s3_data <= s2_data_0 + s2_data_1;
data_msb_s3_i <= data_msb_s3_i_s; s3_ddata <= s2_ddata;
data_delay_s3_i <= data_delay_s3_i_s;
data_sine_s3_i <= 16'hc666 + data_sine_s3_i_s[31:16];
end end
// level 2, second order (A*y2 + B*y) // level 2 - final
ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s3 ( ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2 (
.clk (clk), .clk (clk),
.data_a (data_delay_s3_i), .data_a (s3_data[16:0]),
.data_b (data_sine_s3_i), .data_b (s3_data[16:0]),
.data_p (data_sine_s3_s), .data_p (s4_data2_s),
.ddata_in ({ddata_s3_i, data_msb_s3_i}), .ddata_in ({s3_ddata, s3_data[16:0]}),
.ddata_out ({ddata_s3_s, data_msb_s3_s})); .ddata_out ({s4_ddata_s, s4_data1_s}));
// 2's complement versions
always @(posedge clk) begin always @(posedge clk) begin
ddata_s4 <= ddata_s3_s; s4_data2_p <= s4_data2_s;
data_msb <= data_msb_s3_s; s4_data2_n <= ~s4_data2_s + 1'b1;
data_sine_p <= data_sine_s3_s[31:17]; s4_data1_p <= s4_data1_s;
data_sine_n <= ~data_sine_s3_s[31:17] + 1'b1; s4_data1_n <= ~s4_data1_s + 1'b1;
ddata_out <= ddata_s4; s4_ddata <= s4_ddata_s;
sine <= (data_msb == 1'b1) ? {1'b1, data_sine_n} : {1'b0, data_sine_p}; end
// select partial products
always @(posedge clk) begin
s5_data2_0 <= (s4_data1_p[16] == 1'b1) ? s4_data2_n[31:15] : s4_data2_p[31:15];
s5_data2_1 <= s4_data1_n;
s5_data1 <= s4_data1_p;
s5_ddata <= s4_ddata;
end
// corrected-sine
always @(posedge clk) begin
s6_data2 <= s5_data2_0 + s5_data2_1;
s6_data1 <= s5_data1;
s6_ddata <= s5_ddata;
end
// full-scale
ad_mul #(.DELAY_DATA_WIDTH(1)) i_mul_s3_2 (
.clk (clk),
.data_a (s6_data2),
.data_b (17'h1d08),
.data_p (s7_data2_s),
.ddata_in (1'b0),
.ddata_out ());
ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_s3_1 (
.clk (clk),
.data_a (s6_data1),
.data_b (17'h7fff),
.data_p (s7_data1_s),
.ddata_in (s6_ddata),
.ddata_out (s7_ddata_s));
// corrected sum
always @(posedge clk) begin
s7_data <= s7_data2_s + s7_data1_s;
s7_ddata <= s7_ddata_s;
end
// output registers
always @(posedge clk) begin
sine <= s7_data[30:15];
ddata_out <= s7_ddata;
end end
endmodule endmodule

105
library/common/ad_iqcor.v
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@ -36,6 +36,8 @@
// *************************************************************************** // ***************************************************************************
// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter. // iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter.
`timescale 1ns/100ps
module ad_iqcor ( module ad_iqcor (
// data interface // data interface
@ -77,106 +79,57 @@ module ad_iqcor (
reg p1_valid = 'd0; reg p1_valid = 'd0;
reg [15:0] p1_data_i = 'd0; reg [15:0] p1_data_i = 'd0;
reg [15:0] p1_data_q = 'd0; reg [15:0] p1_data_q = 'd0;
reg p2_valid = 'd0; reg [33:0] p1_data_p = 'd0;
reg p2_sign_i = 'd0;
reg p2_sign_q = 'd0;
reg [14:0] p2_magn_i = 'd0;
reg [14:0] p2_magn_q = 'd0;
reg p3_valid = 'd0;
reg [15:0] p3_data_i = 'd0;
reg [15:0] p3_data_q = 'd0;
reg p4_valid = 'd0;
reg [15:0] p4_data = 'd0;
reg valid_out = 'd0; reg valid_out = 'd0;
reg [15:0] data_out = 'd0; reg [15:0] data_out = 'd0;
// internal signals // internal signals
wire [15:0] p2_data_i_s; wire [33:0] p1_data_p_i_s;
wire [15:0] p2_data_q_s; wire p1_valid_s;
wire p3_valid_s; wire [15:0] p1_data_i_s;
wire [31:0] p3_magn_i_s; wire [33:0] p1_data_p_q_s;
wire p3_sign_i_s; wire [15:0] p1_data_q_s;
wire [31:0] p3_magn_q_s;
wire p3_sign_q_s;
wire [15:0] p3_data_2s_i_p_s;
wire [15:0] p3_data_2s_q_p_s;
wire [15:0] p3_data_2s_i_n_s;
wire [15:0] p3_data_2s_q_n_s;
// apply offsets first
always @(posedge clk) begin
p1_valid <= valid;
p1_data_i <= data_i;
p1_data_q <= data_q;
end
// convert to sign-magnitude
assign p2_data_i_s = ~p1_data_i + 1'b1;
assign p2_data_q_s = ~p1_data_q + 1'b1;
always @(posedge clk) begin
p2_valid <= p1_valid;
p2_sign_i <= p1_data_i[15] ^ iqcor_coeff_1[15];
p2_sign_q <= p1_data_q[15] ^ iqcor_coeff_2[15];
p2_magn_i <= (p1_data_i[15] == 1'b1) ? p2_data_i_s[14:0] : p1_data_i[14:0];
p2_magn_q <= (p1_data_q[15] == 1'b1) ? p2_data_q_s[14:0] : p1_data_q[14:0];
end
// scaling functions - i // scaling functions - i
ad_mul_u16 #(.DELAY_DATA_WIDTH(2)) i_mul_u16_i ( ad_mul #(.DELAY_DATA_WIDTH(17)) i_mul_i (
.clk (clk), .clk (clk),
.data_a ({1'b0, p2_magn_i}), .data_a ({data_i[15], data_i}),
.data_b ({1'b0, iqcor_coeff_1[14:0]}), .data_b ({iqcor_coeff_1[15], iqcor_coeff_1}),
.data_p (p3_magn_i_s), .data_p (p1_data_p_i_s),
.ddata_in ({p2_valid, p2_sign_i}), .ddata_in ({valid, data_i}),
.ddata_out ({p3_valid_s, p3_sign_i_s})); .ddata_out ({p1_valid_s, p1_data_i_s}));
// scaling functions - q // scaling functions - q
ad_mul_u16 #(.DELAY_DATA_WIDTH(1)) i_mul_u16_q ( ad_mul #(.DELAY_DATA_WIDTH(16)) i_mul_q (
.clk (clk), .clk (clk),
.data_a ({1'b0, p2_magn_q}), .data_a ({data_q[15], data_q}),
.data_b ({1'b0, iqcor_coeff_2[14:0]}), .data_b ({iqcor_coeff_2[15], iqcor_coeff_2}),
.data_p (p3_magn_q_s), .data_p (p1_data_p_q_s),
.ddata_in (p2_sign_q), .ddata_in (data_q),
.ddata_out (p3_sign_q_s)); .ddata_out (p1_data_q_s));
// convert to 2s-complements // sum
assign p3_data_2s_i_p_s = {1'b0, p3_magn_i_s[28:14]};
assign p3_data_2s_q_p_s = {1'b0, p3_magn_q_s[28:14]};
assign p3_data_2s_i_n_s = ~p3_data_2s_i_p_s + 1'b1;
assign p3_data_2s_q_n_s = ~p3_data_2s_q_p_s + 1'b1;
always @(posedge clk) begin always @(posedge clk) begin
p3_valid <= p3_valid_s; p1_valid <= p1_valid_s;
p3_data_i <= (p3_sign_i_s == 1'b1) ? p3_data_2s_i_n_s : p3_data_2s_i_p_s; p1_data_i <= p1_data_i_s;
p3_data_q <= (p3_sign_q_s == 1'b1) ? p3_data_2s_q_n_s : p3_data_2s_q_p_s; p1_data_q <= p1_data_q_s;
end p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
// corrected output is sum of two
always @(posedge clk) begin
p4_valid <= p3_valid;
p4_data <= p3_data_i + p3_data_q;
end end
// output registers // output registers
always @(posedge clk) begin always @(posedge clk) begin
valid_out <= p1_valid;
if (iqcor_enable == 1'b1) begin if (iqcor_enable == 1'b1) begin
valid_out <= p4_valid; data_out <= p1_data_p[29:14];
data_out <= p4_data;
end else if (IQSEL == 1) begin end else if (IQSEL == 1) begin
valid_out <= valid; data_out <= p1_data_q;
data_out <= data_q;
end else begin end else begin
valid_out <= valid; data_out <= p1_data_i;
data_out <= data_i;
end end
end end

101
library/common/ad_mul.v Normal file
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@ -0,0 +1,101 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ps/1ps
module ad_mul (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
// data_p = data_a * data_b;
input clk;
input [16:0] data_a;
input [16:0] data_b;
output [33:0] data_p;
// delay interface
input [(DELAY_DATA_WIDTH-1):0] ddata_in;
output [(DELAY_DATA_WIDTH-1):0] ddata_out;
// internal registers
reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0;
reg [(DELAY_DATA_WIDTH-1):0] ddata_out = 'd0;
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
MULT_MACRO #(
.LATENCY (3),
.WIDTH_A (17),
.WIDTH_B (17))
i_mult_macro (
.CE (1'b1),
.RST (1'b0),
.CLK (clk),
.A (data_a),
.B (data_b),
.P (data_p));
endmodule
// ***************************************************************************
// ***************************************************************************

122
library/common/ad_pnmon.v Executable file
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@ -0,0 +1,122 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module ad_pnmon (
// adc interface
adc_clk,
adc_valid_in,
adc_data_in,
adc_data_pn,
// pn out of sync and error
adc_pn_oos,
adc_pn_err);
// parameters
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// adc interface
input adc_clk;
input adc_valid_in;
input [DW:0] adc_data_in;
input [DW:0] adc_data_pn;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg adc_valid_d = 'd0;
reg adc_pn_match_d = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg adc_pn_oos = 'd0;
reg [ 3:0] adc_pn_oos_count = 'd0;
// internal signals
wire adc_pn_match_d_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// make sure data is not 0, sequence will fail.
assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d & adc_pn_match_z;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn oos and counters (16 to clear and set).
always @(posedge adc_clk) begin
adc_valid_d <= adc_valid_in;
adc_pn_match_d <= adc_pn_match_d_s;
adc_pn_match_z <= adc_pn_match_z_s;
if (adc_valid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin
adc_pn_oos <= ~adc_pn_oos;
end
if (adc_pn_update_s == 1'b1) begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
end else begin
adc_pn_oos_count <= 'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

96
library/common/up_adc_channel.v
View File

@ -46,18 +46,17 @@ module up_adc_channel (
adc_clk, adc_clk,
adc_rst, adc_rst,
adc_enable, adc_enable,
adc_lb_enb,
adc_pn_sel,
adc_iqcor_enb, adc_iqcor_enb,
adc_dcfilt_enb, adc_dcfilt_enb,
adc_dfmt_se, adc_dfmt_se,
adc_dfmt_type, adc_dfmt_type,
adc_dfmt_enable, adc_dfmt_enable,
adc_pn_type,
adc_dcfilt_offset, adc_dcfilt_offset,
adc_dcfilt_coeff, adc_dcfilt_coeff,
adc_iqcor_coeff_1, adc_iqcor_coeff_1,
adc_iqcor_coeff_2, adc_iqcor_coeff_2,
adc_pnseq_sel,
adc_data_sel,
adc_pn_err, adc_pn_err,
adc_pn_oos, adc_pn_oos,
adc_or, adc_or,
@ -102,18 +101,17 @@ module up_adc_channel (
input adc_clk; input adc_clk;
input adc_rst; input adc_rst;
output adc_enable; output adc_enable;
output adc_lb_enb;
output adc_pn_sel;
output adc_iqcor_enb; output adc_iqcor_enb;
output adc_dcfilt_enb; output adc_dcfilt_enb;
output adc_dfmt_se; output adc_dfmt_se;
output adc_dfmt_type; output adc_dfmt_type;
output adc_dfmt_enable; output adc_dfmt_enable;
output adc_pn_type;
output [15:0] adc_dcfilt_offset; output [15:0] adc_dcfilt_offset;
output [15:0] adc_dcfilt_coeff; output [15:0] adc_dcfilt_coeff;
output [15:0] adc_iqcor_coeff_1; output [15:0] adc_iqcor_coeff_1;
output [15:0] adc_iqcor_coeff_2; output [15:0] adc_iqcor_coeff_2;
output [ 3:0] adc_pnseq_sel;
output [ 3:0] adc_data_sel;
input adc_pn_err; input adc_pn_err;
input adc_pn_oos; input adc_pn_oos;
input adc_or; input adc_or;
@ -167,6 +165,8 @@ module up_adc_channel (
reg [15:0] up_adc_dcfilt_coeff = 'd0; reg [15:0] up_adc_dcfilt_coeff = 'd0;
reg [15:0] up_adc_iqcor_coeff_1 = 'd0; reg [15:0] up_adc_iqcor_coeff_1 = 'd0;
reg [15:0] up_adc_iqcor_coeff_2 = 'd0; reg [15:0] up_adc_iqcor_coeff_2 = 'd0;
reg [ 3:0] up_adc_pnseq_sel = 'd0;
reg [ 3:0] up_adc_data_sel = 'd0;
reg up_usr_datatype_be = 'd0; reg up_usr_datatype_be = 'd0;
reg up_usr_datatype_signed = 'd0; reg up_usr_datatype_signed = 'd0;
reg [ 7:0] up_usr_datatype_shift = 'd0; reg [ 7:0] up_usr_datatype_shift = 'd0;
@ -176,6 +176,10 @@ module up_adc_channel (
reg [15:0] up_usr_decimation_n = 'd0; reg [15:0] up_usr_decimation_n = 'd0;
reg up_ack = 'd0; reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata = 'd0;
reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0;
reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0;
reg [ 3:0] up_adc_pnseq_sel_m = 'd0;
reg [ 3:0] up_adc_data_sel_m = 'd0;
// internal signals // internal signals
@ -185,6 +189,21 @@ module up_adc_channel (
wire up_adc_pn_oos_s; wire up_adc_pn_oos_s;
wire up_adc_or_s; wire up_adc_or_s;
// 2's complement function
function [15:0] sm2tc;
input [15:0] din;
reg [15:0] dp;
reg [15:0] dn;
reg [15:0] dout;
begin
dp = {1'b0, din[14:0]};
dn = ~dp + 1'b1;
dout = (din[15] == 1'b1) ? dn : dp;
sm2tc = dout;
end
endfunction
// decode block select // decode block select
assign up_sel_s = ((up_addr[13:8] == 6'h01) && (up_addr[7:4] == PCORE_ADC_CHID)) ? up_sel : 1'b0; assign up_sel_s = ((up_addr[13:8] == 6'h01) && (up_addr[7:4] == PCORE_ADC_CHID)) ? up_sel : 1'b0;
@ -210,6 +229,8 @@ module up_adc_channel (
up_adc_dcfilt_coeff <= 'd0; up_adc_dcfilt_coeff <= 'd0;
up_adc_iqcor_coeff_1 <= 'd0; up_adc_iqcor_coeff_1 <= 'd0;
up_adc_iqcor_coeff_2 <= 'd0; up_adc_iqcor_coeff_2 <= 'd0;
up_adc_pnseq_sel <= 'd0;
up_adc_data_sel <= 'd0;
up_usr_datatype_be <= 'd0; up_usr_datatype_be <= 'd0;
up_usr_datatype_signed <= 'd0; up_usr_datatype_signed <= 'd0;
up_usr_datatype_shift <= 'd0; up_usr_datatype_shift <= 'd0;
@ -252,6 +273,10 @@ module up_adc_channel (
up_adc_iqcor_coeff_1 <= up_wdata[31:16]; up_adc_iqcor_coeff_1 <= up_wdata[31:16];
up_adc_iqcor_coeff_2 <= up_wdata[15:0]; up_adc_iqcor_coeff_2 <= up_wdata[15:0];
end end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h6)) begin
up_adc_pnseq_sel <= up_wdata[19:16];
up_adc_data_sel <= up_wdata[3:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8)) begin if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8)) begin
up_usr_datatype_be <= up_wdata[25]; up_usr_datatype_be <= up_wdata[25];
up_usr_datatype_signed <= up_wdata[24]; up_usr_datatype_signed <= up_wdata[24];
@ -276,12 +301,14 @@ module up_adc_channel (
up_ack <= up_sel_s; up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin if (up_sel_s == 1'b1) begin
case (up_addr[3:0]) case (up_addr[3:0])
4'h0: up_rdata <= {20'd0, up_adc_lb_enb, up_adc_pn_sel, up_adc_iqcor_enb, up_adc_dcfilt_enb, 4'h0: up_rdata <= {20'd0, up_adc_lb_enb, up_adc_pn_sel,
up_adc_iqcor_enb, up_adc_dcfilt_enb,
1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable, 1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable,
2'd0, up_adc_pn_type, up_adc_enable}; 2'd0, up_adc_pn_type, up_adc_enable};
4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or}; 4'h1: up_rdata <= {29'd0, up_adc_pn_err, up_adc_pn_oos, up_adc_or};
4'h4: up_rdata <= {up_adc_dcfilt_offset, up_adc_dcfilt_coeff}; 4'h4: up_rdata <= {up_adc_dcfilt_offset, up_adc_dcfilt_coeff};
4'h5: up_rdata <= {up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2}; 4'h5: up_rdata <= {up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2};
4'h6: up_rdata <= {12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel};
4'h8: up_rdata <= {6'd0, adc_usr_datatype_be, adc_usr_datatype_signed, 4'h8: up_rdata <= {6'd0, adc_usr_datatype_be, adc_usr_datatype_signed,
adc_usr_datatype_shift, adc_usr_datatype_total_bits, adc_usr_datatype_shift, adc_usr_datatype_total_bits,
adc_usr_datatype_bits}; adc_usr_datatype_bits};
@ -294,39 +321,70 @@ module up_adc_channel (
end end
end end
// change coefficients to 2's complements
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_iqcor_coeff_tc_1 <= 16'd0;
up_adc_iqcor_coeff_tc_2 <= 16'd0;
end else begin
up_adc_iqcor_coeff_tc_1 <= sm2tc(up_adc_iqcor_coeff_1);
up_adc_iqcor_coeff_tc_2 <= sm2tc(up_adc_iqcor_coeff_2);
end
end
// data/pn sources
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_pnseq_sel_m <= 4'd0;
up_adc_data_sel_m <= 4'd0;
end else begin
case ({up_adc_pn_type, up_adc_pn_sel})
2'b10: up_adc_pnseq_sel_m <= 4'h1;
2'b01: up_adc_pnseq_sel_m <= 4'h9;
default: up_adc_pnseq_sel_m <= up_adc_pnseq_sel;
endcase
if (up_adc_lb_enb == 1'b1) begin
up_adc_data_sel_m <= 4'h1;
end else begin
up_adc_data_sel_m <= up_adc_data_sel;
end
end
end
// adc control & status // adc control & status
up_xfer_cntrl #(.DATA_WIDTH(73)) i_adc_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(78)) i_adc_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_adc_lb_enb, .up_data_cntrl ({ up_adc_iqcor_enb,
up_adc_pn_sel,
up_adc_iqcor_enb,
up_adc_dcfilt_enb, up_adc_dcfilt_enb,
up_adc_dfmt_se, up_adc_dfmt_se,
up_adc_dfmt_type, up_adc_dfmt_type,
up_adc_dfmt_enable, up_adc_dfmt_enable,
up_adc_pn_type,
up_adc_enable, up_adc_enable,
up_adc_dcfilt_offset, up_adc_dcfilt_offset,
up_adc_dcfilt_coeff, up_adc_dcfilt_coeff,
up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_tc_1,
up_adc_iqcor_coeff_2}), up_adc_iqcor_coeff_tc_2,
up_adc_pnseq_sel_m,
up_adc_data_sel_m}),
.up_xfer_done (),
.d_rst (adc_rst), .d_rst (adc_rst),
.d_clk (adc_clk), .d_clk (adc_clk),
.d_data_cntrl ({ adc_lb_enb, .d_data_cntrl ({ adc_iqcor_enb,
adc_pn_sel,
adc_iqcor_enb,
adc_dcfilt_enb, adc_dcfilt_enb,
adc_dfmt_se, adc_dfmt_se,
adc_dfmt_type, adc_dfmt_type,
adc_dfmt_enable, adc_dfmt_enable,
adc_pn_type,
adc_enable, adc_enable,
adc_dcfilt_offset, adc_dcfilt_offset,
adc_dcfilt_coeff, adc_dcfilt_coeff,
adc_iqcor_coeff_1, adc_iqcor_coeff_1,
adc_iqcor_coeff_2})); adc_iqcor_coeff_2,
adc_pnseq_sel,
adc_data_sel}));
up_xfer_status #(.DATA_WIDTH(3)) i_adc_xfer_status ( up_xfer_status #(.DATA_WIDTH(3)) i_adc_xfer_status (
.up_rstn (up_rstn), .up_rstn (up_rstn),

38
library/common/up_adc_common.v
View File

@ -53,13 +53,16 @@ module up_adc_common (
adc_ddr_edgesel, adc_ddr_edgesel,
adc_pin_mode, adc_pin_mode,
adc_status, adc_status,
adc_status_pn_err,
adc_status_pn_oos,
adc_status_or,
adc_status_ovf, adc_status_ovf,
adc_status_unf, adc_status_unf,
adc_clk_ratio, adc_clk_ratio,
// channel interface
up_status_pn_err,
up_status_pn_oos,
up_status_or,
// delay interface // delay interface
delay_clk, delay_clk,
@ -102,7 +105,7 @@ module up_adc_common (
// parameters // parameters
localparam PCORE_VERSION = 32'h00060061; localparam PCORE_VERSION = 32'h00080061;
parameter PCORE_ID = 0; parameter PCORE_ID = 0;
// clock reset // clock reset
@ -117,13 +120,16 @@ module up_adc_common (
output adc_ddr_edgesel; output adc_ddr_edgesel;
output adc_pin_mode; output adc_pin_mode;
input adc_status; input adc_status;
input adc_status_pn_err;
input adc_status_pn_oos;
input adc_status_or;
input adc_status_ovf; input adc_status_ovf;
input adc_status_unf; input adc_status_unf;
input [31:0] adc_clk_ratio; input [31:0] adc_clk_ratio;
// channel interface
input up_status_pn_err;
input up_status_pn_oos;
input up_status_or;
// delay interface // delay interface
input delay_clk; input delay_clk;
@ -192,9 +198,6 @@ module up_adc_common (
wire up_wr_s; wire up_wr_s;
wire up_preset_s; wire up_preset_s;
wire up_mmcm_preset_s; wire up_mmcm_preset_s;
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire up_status_s; wire up_status_s;
wire [31:0] up_adc_clk_count_s; wire [31:0] up_adc_clk_count_s;
wire [ 4:0] up_delay_rdata_s; wire [ 4:0] up_delay_rdata_s;
@ -290,7 +293,7 @@ module up_adc_common (
8'h11: up_rdata <= {29'd0, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; 8'h11: up_rdata <= {29'd0, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode};
8'h15: up_rdata <= up_adc_clk_count_s; 8'h15: up_rdata <= up_adc_clk_count_s;
8'h16: up_rdata <= adc_clk_ratio; 8'h16: up_rdata <= adc_clk_ratio;
8'h17: up_rdata <= {28'd0, up_status_pn_err_s, up_status_pn_oos_s, up_status_or_s, up_status_s}; 8'h17: up_rdata <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata}; 8'h18: up_rdata <= {14'd0, up_delay_sel, up_delay_rwn, up_delay_addr, 3'd0, up_delay_wdata};
8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s}; 8'h19: up_rdata <= {22'd0, up_delay_locked_s, up_delay_status_s, 3'd0, up_delay_rdata_s};
8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata};
@ -321,27 +324,22 @@ module up_adc_common (
.up_data_cntrl ({ up_adc_r1_mode, .up_data_cntrl ({ up_adc_r1_mode,
up_adc_ddr_edgesel, up_adc_ddr_edgesel,
up_adc_pin_mode}), up_adc_pin_mode}),
.up_xfer_done (),
.d_rst (adc_rst), .d_rst (adc_rst),
.d_clk (adc_clk), .d_clk (adc_clk),
.d_data_cntrl ({ adc_r1_mode, .d_data_cntrl ({ adc_r1_mode,
adc_ddr_edgesel, adc_ddr_edgesel,
adc_pin_mode})); adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(6)) i_adc_xfer_status ( up_xfer_status #(.DATA_WIDTH(3)) i_adc_xfer_status (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_status ({up_status_pn_err_s, .up_data_status ({up_status_s,
up_status_pn_oos_s,
up_status_or_s,
up_status_s,
up_status_ovf_s, up_status_ovf_s,
up_status_unf_s}), up_status_unf_s}),
.d_rst (adc_rst), .d_rst (adc_rst),
.d_clk (adc_clk), .d_clk (adc_clk),
.d_data_status ({ adc_status_pn_err, .d_data_status ({ adc_status,
adc_status_pn_oos,
adc_status_or,
adc_status,
adc_status_ovf, adc_status_ovf,
adc_status_unf})); adc_status_unf}));

2
library/common/up_axi.v
View File

@ -37,6 +37,8 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
`timescale 1ns/100ps
module up_axi ( module up_axi (
// reset and clocks // reset and clocks

133
library/common/up_dac_channel.v
View File

@ -51,11 +51,12 @@ module up_dac_channel (
dac_dds_scale_2, dac_dds_scale_2,
dac_dds_init_2, dac_dds_init_2,
dac_dds_incr_2, dac_dds_incr_2,
dac_dds_patt_1, dac_pat_data_1,
dac_dds_patt_2, dac_pat_data_2,
dac_dds_sel, dac_data_sel,
dac_lb_enb, dac_iqcor_enb,
dac_pn_enb, dac_iqcor_coeff_1,
dac_iqcor_coeff_2,
// user controls // user controls
@ -99,11 +100,12 @@ module up_dac_channel (
output [15:0] dac_dds_scale_2; output [15:0] dac_dds_scale_2;
output [15:0] dac_dds_init_2; output [15:0] dac_dds_init_2;
output [15:0] dac_dds_incr_2; output [15:0] dac_dds_incr_2;
output [15:0] dac_dds_patt_1; output [15:0] dac_pat_data_1;
output [15:0] dac_dds_patt_2; output [15:0] dac_pat_data_2;
output [ 3:0] dac_dds_sel; output [ 3:0] dac_data_sel;
output dac_lb_enb; output dac_iqcor_enb;
output dac_pn_enb; output [15:0] dac_iqcor_coeff_1;
output [15:0] dac_iqcor_coeff_2;
// user controls // user controls
@ -141,11 +143,14 @@ module up_dac_channel (
reg [15:0] up_dac_dds_scale_2 = 'd0; reg [15:0] up_dac_dds_scale_2 = 'd0;
reg [15:0] up_dac_dds_init_2 = 'd0; reg [15:0] up_dac_dds_init_2 = 'd0;
reg [15:0] up_dac_dds_incr_2 = 'd0; reg [15:0] up_dac_dds_incr_2 = 'd0;
reg [15:0] up_dac_dds_patt_2 = 'd0; reg [15:0] up_dac_pat_data_2 = 'd0;
reg [15:0] up_dac_dds_patt_1 = 'd0; reg [15:0] up_dac_pat_data_1 = 'd0;
reg up_dac_iqcor_enb = 'd0;
reg up_dac_lb_enb = 'd0; reg up_dac_lb_enb = 'd0;
reg up_dac_pn_enb = 'd0; reg up_dac_pn_enb = 'd0;
reg [ 3:0] up_dac_dds_sel = 'd0; reg [ 3:0] up_dac_data_sel = 'd0;
reg [15:0] up_dac_iqcor_coeff_1 = 'd0;
reg [15:0] up_dac_iqcor_coeff_2 = 'd0;
reg up_usr_datatype_be = 'd0; reg up_usr_datatype_be = 'd0;
reg up_usr_datatype_signed = 'd0; reg up_usr_datatype_signed = 'd0;
reg [ 7:0] up_usr_datatype_shift = 'd0; reg [ 7:0] up_usr_datatype_shift = 'd0;
@ -155,12 +160,30 @@ module up_dac_channel (
reg [15:0] up_usr_interpolation_n = 'd0; reg [15:0] up_usr_interpolation_n = 'd0;
reg up_ack = 'd0; reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata = 'd0;
reg [15:0] up_dac_dds_scale_tc_1 = 'd0;
reg [15:0] up_dac_dds_scale_tc_2 = 'd0;
reg [ 3:0] up_dac_data_sel_m = 'd0;
// internal signals // internal signals
wire up_sel_s; wire up_sel_s;
wire up_wr_s; wire up_wr_s;
// 2's complement function
function [15:0] sm2tc;
input [15:0] din;
reg [15:0] dp;
reg [15:0] dn;
reg [15:0] dout;
begin
dp = {1'b0, din[14:0]};
dn = ~dp + 1'b1;
dout = (din[15] == 1'b1) ? dn : dp;
sm2tc = dout;
end
endfunction
// decode block select // decode block select
assign up_sel_s = ((up_addr[13:8] == 6'h11) && (up_addr[7:4] == PCORE_DAC_CHID)) ? up_sel : 1'b0; assign up_sel_s = ((up_addr[13:8] == 6'h11) && (up_addr[7:4] == PCORE_DAC_CHID)) ? up_sel : 1'b0;
@ -176,11 +199,14 @@ module up_dac_channel (
up_dac_dds_scale_2 <= 'd0; up_dac_dds_scale_2 <= 'd0;
up_dac_dds_init_2 <= 'd0; up_dac_dds_init_2 <= 'd0;
up_dac_dds_incr_2 <= 'd0; up_dac_dds_incr_2 <= 'd0;
up_dac_dds_patt_2 <= 'd0; up_dac_pat_data_2 <= 'd0;
up_dac_dds_patt_1 <= 'd0; up_dac_pat_data_1 <= 'd0;
up_dac_iqcor_enb <= 'd0;
up_dac_lb_enb <= 'd0; up_dac_lb_enb <= 'd0;
up_dac_pn_enb <= 'd0; up_dac_pn_enb <= 'd0;
up_dac_dds_sel <= 'd0; up_dac_data_sel <= 'd0;
up_dac_iqcor_coeff_1 <= 'd0;
up_dac_iqcor_coeff_2 <= 'd0;
up_usr_datatype_be <= 'd0; up_usr_datatype_be <= 'd0;
up_usr_datatype_signed <= 'd0; up_usr_datatype_signed <= 'd0;
up_usr_datatype_shift <= 'd0; up_usr_datatype_shift <= 'd0;
@ -204,15 +230,20 @@ module up_dac_channel (
up_dac_dds_incr_2 <= up_wdata[15:0]; up_dac_dds_incr_2 <= up_wdata[15:0];
end end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h4)) begin if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h4)) begin
up_dac_dds_patt_2 <= up_wdata[31:16]; up_dac_pat_data_2 <= up_wdata[31:16];
up_dac_dds_patt_1 <= up_wdata[15:0]; up_dac_pat_data_1 <= up_wdata[15:0];
end end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h5)) begin if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h5)) begin
up_dac_iqcor_enb <= up_wdata[2];
up_dac_lb_enb <= up_wdata[1]; up_dac_lb_enb <= up_wdata[1];
up_dac_pn_enb <= up_wdata[0]; up_dac_pn_enb <= up_wdata[0];
end end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h6)) begin if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h6)) begin
up_dac_dds_sel <= up_wdata[3:0]; up_dac_data_sel <= up_wdata[3:0];
end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h7)) begin
up_dac_iqcor_coeff_1 <= up_wdata[31:16];
up_dac_iqcor_coeff_2 <= up_wdata[15:0];
end end
if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8)) begin if ((up_wr_s == 1'b1) && (up_addr[3:0] == 4'h8)) begin
up_usr_datatype_be <= up_wdata[25]; up_usr_datatype_be <= up_wdata[25];
@ -242,9 +273,10 @@ module up_dac_channel (
4'h1: up_rdata <= {up_dac_dds_init_1, up_dac_dds_incr_1}; 4'h1: up_rdata <= {up_dac_dds_init_1, up_dac_dds_incr_1};
4'h2: up_rdata <= {16'd0, up_dac_dds_scale_2}; 4'h2: up_rdata <= {16'd0, up_dac_dds_scale_2};
4'h3: up_rdata <= {up_dac_dds_init_2, up_dac_dds_incr_2}; 4'h3: up_rdata <= {up_dac_dds_init_2, up_dac_dds_incr_2};
4'h4: up_rdata <= {up_dac_dds_patt_2, up_dac_dds_patt_1}; 4'h4: up_rdata <= {up_dac_pat_data_2, up_dac_pat_data_1};
4'h5: up_rdata <= {30'd0, up_dac_lb_enb, up_dac_pn_enb}; 4'h5: up_rdata <= {29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb};
4'h6: up_rdata <= {28'd0, up_dac_dds_sel}; 4'h6: up_rdata <= {28'd0, up_dac_data_sel_m};
4'h7: up_rdata <= {up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2};
4'h8: up_rdata <= {6'd0, dac_usr_datatype_be, dac_usr_datatype_signed, 4'h8: up_rdata <= {6'd0, dac_usr_datatype_be, dac_usr_datatype_signed,
dac_usr_datatype_shift, dac_usr_datatype_total_bits, dac_usr_datatype_shift, dac_usr_datatype_total_bits,
dac_usr_datatype_bits}; dac_usr_datatype_bits};
@ -257,35 +289,64 @@ module up_dac_channel (
end end
end end
// change coefficients to 2's complements
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_dds_scale_tc_1 <= 16'd0;
up_dac_dds_scale_tc_2 <= 16'd0;
end else begin
up_dac_dds_scale_tc_1 <= sm2tc(up_dac_dds_scale_1);
up_dac_dds_scale_tc_2 <= sm2tc(up_dac_dds_scale_2);
end
end
// backward compatibility
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dac_data_sel_m <= 4'd0;
end else begin
case ({up_dac_lb_enb, up_dac_pn_enb})
2'b10: up_dac_data_sel_m <= 4'h8;
2'b01: up_dac_data_sel_m <= 4'h9;
default: up_dac_data_sel_m <= up_dac_data_sel;
endcase
end
end
// dac control & status // dac control & status
up_xfer_cntrl #(.DATA_WIDTH(134)) i_dac_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(165)) i_dac_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_dac_dds_scale_1, .up_data_cntrl ({ up_dac_iqcor_enb,
up_dac_iqcor_coeff_1,
up_dac_iqcor_coeff_2,
up_dac_dds_scale_tc_1,
up_dac_dds_init_1, up_dac_dds_init_1,
up_dac_dds_incr_1, up_dac_dds_incr_1,
up_dac_dds_scale_2, up_dac_dds_scale_tc_2,
up_dac_dds_init_2, up_dac_dds_init_2,
up_dac_dds_incr_2, up_dac_dds_incr_2,
up_dac_dds_patt_1, up_dac_pat_data_1,
up_dac_dds_patt_2, up_dac_pat_data_2,
up_dac_lb_enb, up_dac_data_sel_m}),
up_dac_pn_enb, .up_xfer_done (),
up_dac_dds_sel}),
.d_rst (dac_rst), .d_rst (dac_rst),
.d_clk (dac_clk), .d_clk (dac_clk),
.d_data_cntrl ({ dac_dds_scale_1, .d_data_cntrl ({ dac_iqcor_enb,
dac_iqcor_coeff_1,
dac_iqcor_coeff_2,
dac_dds_scale_1,
dac_dds_init_1, dac_dds_init_1,
dac_dds_incr_1, dac_dds_incr_1,
dac_dds_scale_2, dac_dds_scale_2,
dac_dds_init_2, dac_dds_init_2,
dac_dds_incr_2, dac_dds_incr_2,
dac_dds_patt_1, dac_pat_data_1,
dac_dds_patt_2, dac_pat_data_2,
dac_lb_enb, dac_data_sel}));
dac_pn_enb,
dac_dds_sel}));
endmodule endmodule

58
library/common/up_dac_common.v
View File

@ -49,13 +49,12 @@ module up_dac_common (
dac_clk, dac_clk,
dac_rst, dac_rst,
dac_enable, dac_sync,
dac_frame, dac_frame,
dac_par_type, dac_par_type,
dac_par_enb, dac_par_enb,
dac_r1_mode, dac_r1_mode,
dac_datafmt, dac_datafmt,
dac_datasel,
dac_datarate, dac_datarate,
dac_status, dac_status,
dac_status_ovf, dac_status_ovf,
@ -92,7 +91,7 @@ module up_dac_common (
// parameters // parameters
localparam PCORE_VERSION = 32'h00070061; localparam PCORE_VERSION = 32'h00080061;
parameter PCORE_ID = 0; parameter PCORE_ID = 0;
// mmcm reset // mmcm reset
@ -103,13 +102,12 @@ module up_dac_common (
input dac_clk; input dac_clk;
output dac_rst; output dac_rst;
output dac_enable; output dac_sync;
output dac_frame; output dac_frame;
output dac_par_type; output dac_par_type;
output dac_par_enb; output dac_par_enb;
output dac_r1_mode; output dac_r1_mode;
output dac_datafmt; output dac_datafmt;
output [ 3:0] dac_datasel;
output [ 7:0] dac_datarate; output [ 7:0] dac_datarate;
input dac_status; input dac_status;
input dac_status_ovf; input dac_status_ovf;
@ -149,12 +147,11 @@ module up_dac_common (
reg [31:0] up_scratch = 'd0; reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0; reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0; reg up_resetn = 'd0;
reg up_dac_enable = 'd0; reg up_dac_sync = 'd0;
reg up_dac_par_type = 'd0; reg up_dac_par_type = 'd0;
reg up_dac_par_enb = 'd0; reg up_dac_par_enb = 'd0;
reg up_dac_r1_mode = 'd0; reg up_dac_r1_mode = 'd0;
reg up_dac_datafmt = 'd0; reg up_dac_datafmt = 'd0;
reg [ 3:0] up_dac_datasel = 'd0;
reg [ 7:0] up_dac_datarate = 'd0; reg [ 7:0] up_dac_datarate = 'd0;
reg up_dac_frame = 'd0; reg up_dac_frame = 'd0;
reg up_drp_sel_t = 'd0; reg up_drp_sel_t = 'd0;
@ -166,6 +163,10 @@ module up_dac_common (
reg [ 7:0] up_usr_chanmax = 'd0; reg [ 7:0] up_usr_chanmax = 'd0;
reg up_ack = 'd0; reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0; reg [31:0] up_rdata = 'd0;
reg dac_sync_d = 'd0;
reg dac_sync_2d = 'd0;
reg [ 5:0] dac_sync_count = 'd0;
reg dac_sync = 'd0;
reg dac_frame_d = 'd0; reg dac_frame_d = 'd0;
reg dac_frame_2d = 'd0; reg dac_frame_2d = 'd0;
reg dac_frame = 'd0; reg dac_frame = 'd0;
@ -176,9 +177,11 @@ module up_dac_common (
wire up_wr_s; wire up_wr_s;
wire up_preset_s; wire up_preset_s;
wire up_mmcm_preset_s; wire up_mmcm_preset_s;
wire up_xfer_done_s;
wire up_status_s; wire up_status_s;
wire up_status_ovf_s; wire up_status_ovf_s;
wire up_status_unf_s; wire up_status_unf_s;
wire dac_sync_s;
wire dac_frame_s; wire dac_frame_s;
wire [31:0] up_dac_clk_count_s; wire [31:0] up_dac_clk_count_s;
wire [15:0] up_drp_rdata_s; wire [15:0] up_drp_rdata_s;
@ -199,12 +202,11 @@ module up_dac_common (
up_scratch <= 'd0; up_scratch <= 'd0;
up_mmcm_resetn <= 'd0; up_mmcm_resetn <= 'd0;
up_resetn <= 'd0; up_resetn <= 'd0;
up_dac_enable <= 'd0; up_dac_sync <= 'd0;
up_dac_par_type <= 'd0; up_dac_par_type <= 'd0;
up_dac_par_enb <= 'd0; up_dac_par_enb <= 'd0;
up_dac_r1_mode <= 'd0; up_dac_r1_mode <= 'd0;
up_dac_datafmt <= 'd0; up_dac_datafmt <= 'd0;
up_dac_datasel <= 'd0;
up_dac_datarate <= 'd0; up_dac_datarate <= 'd0;
up_dac_frame <= 'd0; up_dac_frame <= 'd0;
up_drp_sel_t <= 'd0; up_drp_sel_t <= 'd0;
@ -222,20 +224,27 @@ module up_dac_common (
up_mmcm_resetn <= up_wdata[1]; up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0]; up_resetn <= up_wdata[0];
end end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h11)) begin if (up_dac_sync == 1'b1) begin
up_dac_enable <= up_wdata[0]; if (up_xfer_done_s == 1'b1) begin
up_dac_sync <= 1'b0;
end
end else if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h11)) begin
up_dac_sync <= up_wdata[0];
end end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h12)) begin if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h12)) begin
up_dac_par_type <= up_wdata[7]; up_dac_par_type <= up_wdata[7];
up_dac_par_enb <= up_wdata[6]; up_dac_par_enb <= up_wdata[6];
up_dac_r1_mode <= up_wdata[5]; up_dac_r1_mode <= up_wdata[5];
up_dac_datafmt <= up_wdata[4]; up_dac_datafmt <= up_wdata[4];
up_dac_datasel <= up_wdata[3:0];
end end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h13)) begin if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h13)) begin
up_dac_datarate <= up_wdata[7:0]; up_dac_datarate <= up_wdata[7:0];
end end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h14)) begin if (up_dac_frame == 1'b1) begin
if (up_xfer_done_s == 1'b1) begin
up_dac_frame <= 1'b0;
end
end else if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h14)) begin
up_dac_frame <= up_wdata[0]; up_dac_frame <= up_wdata[0];
end end
if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h1c)) begin if ((up_wr_s == 1'b1) && (up_addr[7:0] == 8'h1c)) begin
@ -274,9 +283,9 @@ module up_dac_common (
8'h01: up_rdata <= PCORE_ID; 8'h01: up_rdata <= PCORE_ID;
8'h02: up_rdata <= up_scratch; 8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn};
8'h11: up_rdata <= {31'd0, up_dac_enable}; 8'h11: up_rdata <= {31'd0, up_dac_sync};
8'h12: up_rdata <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, 8'h12: up_rdata <= {24'd0, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode,
up_dac_datafmt, up_dac_datasel}; up_dac_datafmt, 4'd0};
8'h13: up_rdata <= {24'd0, up_dac_datarate}; 8'h13: up_rdata <= {24'd0, up_dac_datarate};
8'h14: up_rdata <= {31'd0, up_dac_frame}; 8'h14: up_rdata <= {31'd0, up_dac_frame};
8'h15: up_rdata <= up_dac_clk_count_s; 8'h15: up_rdata <= up_dac_clk_count_s;
@ -302,26 +311,25 @@ module up_dac_common (
// dac control & status // dac control & status
up_xfer_cntrl #(.DATA_WIDTH(18)) i_dac_xfer_cntrl ( up_xfer_cntrl #(.DATA_WIDTH(14)) i_dac_xfer_cntrl (
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_data_cntrl ({ up_dac_enable, .up_data_cntrl ({ up_dac_sync,
up_dac_frame, up_dac_frame,
up_dac_par_type, up_dac_par_type,
up_dac_par_enb, up_dac_par_enb,
up_dac_r1_mode, up_dac_r1_mode,
up_dac_datafmt, up_dac_datafmt,
up_dac_datasel,
up_dac_datarate}), up_dac_datarate}),
.up_xfer_done (up_xfer_done_s),
.d_rst (dac_rst), .d_rst (dac_rst),
.d_clk (dac_clk), .d_clk (dac_clk),
.d_data_cntrl ({ dac_enable, .d_data_cntrl ({ dac_sync_s,
dac_frame_s, dac_frame_s,
dac_par_type, dac_par_type,
dac_par_enb, dac_par_enb,
dac_r1_mode, dac_r1_mode,
dac_datafmt, dac_datafmt,
dac_datasel,
dac_datarate})); dac_datarate}));
up_xfer_status #(.DATA_WIDTH(3)) i_dac_xfer_status ( up_xfer_status #(.DATA_WIDTH(3)) i_dac_xfer_status (
@ -336,9 +344,17 @@ module up_dac_common (
dac_status_ovf, dac_status_ovf,
dac_status_unf})); dac_status_unf}));
// frame needs to be a pulse // generate frame and enable
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
dac_sync_d <= dac_sync_s;
dac_sync_2d <= dac_sync_d;
if (dac_sync_count[5] == 1'b1) begin
dac_sync_count <= dac_sync_count + 1'b1;
end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin
dac_sync_count <= 6'h20;
end
dac_sync <= dac_sync_count[5];
dac_frame_d <= dac_frame_s; dac_frame_d <= dac_frame_s;
dac_frame_2d <= dac_frame_d; dac_frame_2d <= dac_frame_d;
dac_frame <= dac_frame_d & ~dac_frame_2d; dac_frame <= dac_frame_d & ~dac_frame_2d;

5
library/common/up_xfer_cntrl.v
View File

@ -46,6 +46,7 @@ module up_xfer_cntrl (
up_rstn, up_rstn,
up_clk, up_clk,
up_data_cntrl, up_data_cntrl,
up_xfer_done,
// device interface // device interface
@ -63,6 +64,7 @@ module up_xfer_cntrl (
input up_rstn; input up_rstn;
input up_clk; input up_clk;
input [DW:0] up_data_cntrl; input [DW:0] up_data_cntrl;
output up_xfer_done;
// device interface // device interface
@ -73,6 +75,7 @@ module up_xfer_cntrl (
// internal registers // internal registers
reg [ 5:0] up_xfer_count = 'd0; reg [ 5:0] up_xfer_count = 'd0;
reg up_xfer_done = 'd0;
reg up_xfer_toggle = 'd0; reg up_xfer_toggle = 'd0;
reg [DW:0] up_xfer_data = 'd0; reg [DW:0] up_xfer_data = 'd0;
reg d_xfer_toggle_m1 = 'd0; reg d_xfer_toggle_m1 = 'd0;
@ -89,10 +92,12 @@ module up_xfer_cntrl (
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin if (up_rstn == 1'b0) begin
up_xfer_count <= 'd0; up_xfer_count <= 'd0;
up_xfer_done <= 'd0;
up_xfer_toggle <= 'd0; up_xfer_toggle <= 'd0;
up_xfer_data <= 'd0; up_xfer_data <= 'd0;
end else begin end else begin
up_xfer_count <= up_xfer_count + 1'd1; up_xfer_count <= up_xfer_count + 1'd1;
up_xfer_done <= (up_xfer_count == 6'd1) ? 1'b1 : 1'b0;
if (up_xfer_count == 6'd1) begin if (up_xfer_count == 6'd1) begin
up_xfer_toggle <= ~up_xfer_toggle; up_xfer_toggle <= ~up_xfer_toggle;
up_xfer_data <= up_data_cntrl; up_xfer_data <= up_data_cntrl;