diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v
index fb36a65b3..b5a0dda8f 100644
--- a/library/axi_dmac/axi_dmac.v
+++ b/library/axi_dmac/axi_dmac.v
@@ -2,9 +2,9 @@
 // ***************************************************************************
 // Copyright 2013(c) Analog Devices, Inc.
 //  Author: Lars-Peter Clausen <lars@metafoo.de>
-// 
+//
 // All rights reserved.
-// 
+//
 // Redistribution and use in source and binary forms, with or without modification,
 // are permitted provided that the following conditions are met:
 //     - Redistributions of source code must retain the above copyright
@@ -22,16 +22,16 @@
 //       patent holders to use this software.
 //     - Use of the software either in source or binary form, must be run
 //       on or directly connected to an Analog Devices Inc. component.
-//    
+//
 // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
 // PARTICULAR PURPOSE ARE DISCLAIMED.
 //
 // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 // ***************************************************************************
 // ***************************************************************************
@@ -178,7 +178,7 @@ parameter ID = 0;
 parameter DMA_DATA_WIDTH_SRC = 64;
 parameter DMA_DATA_WIDTH_DEST = 64;
 parameter DMA_LENGTH_WIDTH = 24;
-parameter 2D_TRANSFER = 1;
+parameter DMA_DMA_2D_TRANSFER = 1;
 
 parameter ASYNC_CLK_REQ_SRC = 1;
 parameter ASYNC_CLK_SRC_DEST = 1;
@@ -421,9 +421,9 @@ begin
 		12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
 		12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
 		12'h106: up_rdata <= up_dma_x_length;
-		12'h107: up_rdata <= 2D_TRANSFER ? up_dma_y_length : 'h00;
-		12'h108: up_rdata <= 2D_TRANSFER ? up_dma_dest_stride : 'h00;
-		12'h109: up_rdata <= 2D_TRANSFER ? up_dma_src_stride : 'h00;
+		12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00;
+		12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00;
+		12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00;
 		12'h10a: up_rdata <= up_transfer_done_bitmap;
 		12'h10b: up_rdata <= up_transfer_id_eot;
 		12'h10c: up_rdata <= 'h00; // Status
@@ -469,7 +469,7 @@ assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
 assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
 
 
-generate if (2D_TRANSFER == 1) begin
+generate if (DMA_2D_TRANSFER == 1) begin
 
 dmac_2d_transfer #(
 	.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
@@ -544,13 +544,13 @@ dmac_request_arb #(
 
 	.eot(dma_req_eot),
 
-	
+
 	.m_dest_axi_aclk(m_dest_axi_aclk),
 	.m_dest_axi_aresetn(m_dest_axi_aresetn),
 	.m_src_axi_aclk(m_src_axi_aclk),
 	.m_src_axi_aresetn(m_src_axi_aresetn),
 
-	
+
 	.m_axi_awaddr(m_dest_axi_awaddr),
 	.m_axi_awlen(m_dest_axi_awlen),
 	.m_axi_awsize(m_dest_axi_awsize),
@@ -560,19 +560,19 @@ dmac_request_arb #(
 	.m_axi_awvalid(m_dest_axi_awvalid),
 	.m_axi_awready(m_dest_axi_awready),
 
-	
+
 	.m_axi_wdata(m_dest_axi_wdata),
 	.m_axi_wstrb(m_dest_axi_wstrb),
 	.m_axi_wready(m_dest_axi_wready),
 	.m_axi_wvalid(m_dest_axi_wvalid),
 	.m_axi_wlast(m_dest_axi_wlast),
 
-	
+
 	.m_axi_bvalid(m_dest_axi_bvalid),
 	.m_axi_bresp(m_dest_axi_bresp),
 	.m_axi_bready(m_dest_axi_bready),
 
-	
+
 	.m_axi_arready(m_src_axi_arready),
 	.m_axi_arvalid(m_src_axi_arvalid),
 	.m_axi_araddr(m_src_axi_araddr),
@@ -582,13 +582,13 @@ dmac_request_arb #(
 	.m_axi_arprot(m_src_axi_arprot),
 	.m_axi_arcache(m_src_axi_arcache),
 
-	
+
 	.m_axi_rdata(m_src_axi_rdata),
 	.m_axi_rready(m_src_axi_rready),
 	.m_axi_rvalid(m_src_axi_rvalid),
 	.m_axi_rresp(m_src_axi_rresp),
 
-	
+
 	.s_axis_aclk(s_axis_aclk),
 	.s_axis_ready(s_axis_ready),
 	.s_axis_valid(s_axis_valid),
@@ -596,7 +596,7 @@ dmac_request_arb #(
 	.s_axis_user(s_axis_user),
 	.s_axis_xfer_req(s_axis_xfer_req),
 
-	
+
 	.m_axis_aclk(m_axis_aclk),
 	.m_axis_ready(m_axis_ready),
 	.m_axis_valid(m_axis_valid),
@@ -612,7 +612,7 @@ dmac_request_arb #(
 	.fifo_wr_sync(fifo_wr_sync),
 	.fifo_wr_xfer_req(fifo_wr_xfer_req),
 
-	
+
 	.fifo_rd_clk(fifo_rd_clk),
 	.fifo_rd_en(fifo_rd_en),
 	.fifo_rd_valid(fifo_rd_valid),
diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl
index 2d0732dc8..111674246 100755
--- a/library/axi_dmac/axi_dmac_hw.tcl
+++ b/library/axi_dmac/axi_dmac_hw.tcl
@@ -52,33 +52,33 @@ set_parameter_property ID TYPE INTEGER
 set_parameter_property ID UNITS None
 set_parameter_property ID HDL_PARAMETER true
 
-add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0
-set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
-set_parameter_property C_DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC
-set_parameter_property C_DMA_DATA_WIDTH_SRC TYPE INTEGER
-set_parameter_property C_DMA_DATA_WIDTH_SRC UNITS None
-set_parameter_property C_DMA_DATA_WIDTH_SRC HDL_PARAMETER true
+add_parameter DMA_DATA_WIDTH_SRC INTEGER 0
+set_parameter_property DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
+set_parameter_property DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC
+set_parameter_property DMA_DATA_WIDTH_SRC TYPE INTEGER
+set_parameter_property DMA_DATA_WIDTH_SRC UNITS None
+set_parameter_property DMA_DATA_WIDTH_SRC HDL_PARAMETER true
 
-add_parameter C_DMA_DATA_WIDTH_DEST INTEGER 0
-set_parameter_property C_DMA_DATA_WIDTH_DEST DEFAULT_VALUE 64
-set_parameter_property C_DMA_DATA_WIDTH_DEST DISPLAY_NAME C_DMA_DATA_WIDTH_DEST
-set_parameter_property C_DMA_DATA_WIDTH_DEST TYPE INTEGER
-set_parameter_property C_DMA_DATA_WIDTH_DEST UNITS None
-set_parameter_property C_DMA_DATA_WIDTH_DEST HDL_PARAMETER true
+add_parameter DMA_DATA_WIDTH_DEST INTEGER 0
+set_parameter_property DMA_DATA_WIDTH_DEST DEFAULT_VALUE 64
+set_parameter_property DMA_DATA_WIDTH_DEST DISPLAY_NAME C_DMA_DATA_WIDTH_DEST
+set_parameter_property DMA_DATA_WIDTH_DEST TYPE INTEGER
+set_parameter_property DMA_DATA_WIDTH_DEST UNITS None
+set_parameter_property DMA_DATA_WIDTH_DEST HDL_PARAMETER true
 
-add_parameter C_DMA_LENGTH_WIDTH INTEGER 0
-set_parameter_property C_DMA_LENGTH_WIDTH DEFAULT_VALUE 14
-set_parameter_property C_DMA_LENGTH_WIDTH DISPLAY_NAME C_DMA_LENGTH_WIDTH
-set_parameter_property C_DMA_LENGTH_WIDTH TYPE INTEGER
-set_parameter_property C_DMA_LENGTH_WIDTH UNITS None
-set_parameter_property C_DMA_LENGTH_WIDTH HDL_PARAMETER true
+add_parameter DMA_LENGTH_WIDTH INTEGER 0
+set_parameter_property DMA_LENGTH_WIDTH DEFAULT_VALUE 14
+set_parameter_property DMA_LENGTH_WIDTH DISPLAY_NAME C_DMA_LENGTH_WIDTH
+set_parameter_property DMA_LENGTH_WIDTH TYPE INTEGER
+set_parameter_property DMA_LENGTH_WIDTH UNITS None
+set_parameter_property DMA_LENGTH_WIDTH HDL_PARAMETER true
 
-add_parameter C_2D_TRANSFER INTEGER 0
-set_parameter_property C_2D_TRANSFER DEFAULT_VALUE 1
-set_parameter_property C_2D_TRANSFER DISPLAY_NAME C_2D_TRANSFER
-set_parameter_property C_2D_TRANSFER TYPE INTEGER
-set_parameter_property C_2D_TRANSFER UNITS None
-set_parameter_property C_2D_TRANSFER HDL_PARAMETER true
+add_parameter DMA_2D_TRANSFER INTEGER 0
+set_parameter_property DMA_2D_TRANSFER DEFAULT_VALUE 1
+set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME C_DMA_2D_TRANSFER
+set_parameter_property DMA_2D_TRANSFER TYPE INTEGER
+set_parameter_property DMA_2D_TRANSFER UNITS None
+set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
 
 add_parameter ASYNC_CLK_REQ_SRC INTEGER 0
 set_parameter_property ASYNC_CLK_REQ_SRC DEFAULT_VALUE 1
@@ -101,54 +101,54 @@ set_parameter_property ASYNC_CLK_DEST_REQ TYPE INTEGER
 set_parameter_property ASYNC_CLK_DEST_REQ UNITS None
 set_parameter_property ASYNC_CLK_DEST_REQ HDL_PARAMETER true
 
-add_parameter C_AXI_SLICE_DEST INTEGER 0
-set_parameter_property C_AXI_SLICE_DEST DEFAULT_VALUE 0
-set_parameter_property C_AXI_SLICE_DEST DISPLAY_NAME C_AXI_SLICE_DEST
-set_parameter_property C_AXI_SLICE_DEST TYPE INTEGER
-set_parameter_property C_AXI_SLICE_DEST UNITS None
-set_parameter_property C_AXI_SLICE_DEST HDL_PARAMETER true
+add_parameter AXI_SLICE_DEST INTEGER 0
+set_parameter_property AXI_SLICE_DEST DEFAULT_VALUE 0
+set_parameter_property AXI_SLICE_DEST DISPLAY_NAME C_AXI_SLICE_DEST
+set_parameter_property AXI_SLICE_DEST TYPE INTEGER
+set_parameter_property AXI_SLICE_DEST UNITS None
+set_parameter_property AXI_SLICE_DEST HDL_PARAMETER true
 
-add_parameter C_AXI_SLICE_SRC INTEGER 0
-set_parameter_property C_AXI_SLICE_SRC DEFAULT_VALUE 0
-set_parameter_property C_AXI_SLICE_SRC DISPLAY_NAME C_AXI_SLICE_SRC
-set_parameter_property C_AXI_SLICE_SRC TYPE INTEGER
-set_parameter_property C_AXI_SLICE_SRC UNITS None
-set_parameter_property C_AXI_SLICE_SRC HDL_PARAMETER true
+add_parameter AXI_SLICE_SRC INTEGER 0
+set_parameter_property AXI_SLICE_SRC DEFAULT_VALUE 0
+set_parameter_property AXI_SLICE_SRC DISPLAY_NAME C_AXI_SLICE_SRC
+set_parameter_property AXI_SLICE_SRC TYPE INTEGER
+set_parameter_property AXI_SLICE_SRC UNITS None
+set_parameter_property AXI_SLICE_SRC HDL_PARAMETER true
 
-add_parameter C_SYNC_TRANSFER_START INTEGER 0
-set_parameter_property C_SYNC_TRANSFER_START DEFAULT_VALUE 0
-set_parameter_property C_SYNC_TRANSFER_START DISPLAY_NAME C_SYNC_TRANSFER_START
-set_parameter_property C_SYNC_TRANSFER_START TYPE INTEGER
-set_parameter_property C_SYNC_TRANSFER_START UNITS None
-set_parameter_property C_SYNC_TRANSFER_START HDL_PARAMETER true
+add_parameter SYNC_TRANSFER_START INTEGER 0
+set_parameter_property SYNC_TRANSFER_START DEFAULT_VALUE 0
+set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME C_SYNC_TRANSFER_START
+set_parameter_property SYNC_TRANSFER_START TYPE INTEGER
+set_parameter_property SYNC_TRANSFER_START UNITS None
+set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
 
-add_parameter C_CYCLIC INTEGER 0
-set_parameter_property C_CYCLIC DEFAULT_VALUE 1
-set_parameter_property C_CYCLIC DISPLAY_NAME C_CYCLIC
-set_parameter_property C_CYCLIC TYPE INTEGER
-set_parameter_property C_CYCLIC UNITS None
-set_parameter_property C_CYCLIC HDL_PARAMETER true
+add_parameter CYCLIC INTEGER 0
+set_parameter_property CYCLIC DEFAULT_VALUE 1
+set_parameter_property CYCLIC DISPLAY_NAME C_CYCLIC
+set_parameter_property CYCLIC TYPE INTEGER
+set_parameter_property CYCLIC UNITS None
+set_parameter_property CYCLIC HDL_PARAMETER true
 
-add_parameter C_DMA_TYPE_DEST INTEGER 0
-set_parameter_property C_DMA_TYPE_DEST DEFAULT_VALUE 0
-set_parameter_property C_DMA_TYPE_DEST DISPLAY_NAME C_DMA_TYPE_DEST
-set_parameter_property C_DMA_TYPE_DEST TYPE INTEGER
-set_parameter_property C_DMA_TYPE_DEST UNITS None
-set_parameter_property C_DMA_TYPE_DEST HDL_PARAMETER true
+add_parameter DMA_TYPE_DEST INTEGER 0
+set_parameter_property DMA_TYPE_DEST DEFAULT_VALUE 0
+set_parameter_property DMA_TYPE_DEST DISPLAY_NAME C_DMA_TYPE_DEST
+set_parameter_property DMA_TYPE_DEST TYPE INTEGER
+set_parameter_property DMA_TYPE_DEST UNITS None
+set_parameter_property DMA_TYPE_DEST HDL_PARAMETER true
 
-add_parameter C_DMA_TYPE_SRC INTEGER 0
-set_parameter_property C_DMA_TYPE_SRC DEFAULT_VALUE 2
-set_parameter_property C_DMA_TYPE_SRC DISPLAY_NAME C_DMA_TYPE_SRC
-set_parameter_property C_DMA_TYPE_SRC TYPE INTEGER
-set_parameter_property C_DMA_TYPE_SRC UNITS None
-set_parameter_property C_DMA_TYPE_SRC HDL_PARAMETER true
+add_parameter DMA_TYPE_SRC INTEGER 0
+set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2
+set_parameter_property DMA_TYPE_SRC DISPLAY_NAME C_DMA_TYPE_SRC
+set_parameter_property DMA_TYPE_SRC TYPE INTEGER
+set_parameter_property DMA_TYPE_SRC UNITS None
+set_parameter_property DMA_TYPE_SRC HDL_PARAMETER true
 
-add_parameter C_FIFO_SIZE INTEGER 0 "In bursts"
-set_parameter_property C_FIFO_SIZE DEFAULT_VALUE 4
-set_parameter_property C_FIFO_SIZE DISPLAY_NAME C_FIFO_SIZE
-set_parameter_property C_FIFO_SIZE TYPE INTEGER
-set_parameter_property C_FIFO_SIZE UNITS None
-set_parameter_property C_FIFO_SIZE HDL_PARAMETER true
+add_parameter FIFO_SIZE INTEGER 0 "In bursts"
+set_parameter_property FIFO_SIZE DEFAULT_VALUE 4
+set_parameter_property FIFO_SIZE DISPLAY_NAME C_FIFO_SIZE
+set_parameter_property FIFO_SIZE TYPE INTEGER
+set_parameter_property FIFO_SIZE UNITS None
+set_parameter_property FIFO_SIZE HDL_PARAMETER true
 
 # axi4 slave
 
@@ -199,7 +199,7 @@ proc axi_dmac_elaborate {} {
 
   # axi4 destination/source
 
-  if {[get_parameter_value C_DMA_TYPE_DEST] == 0} {
+  if {[get_parameter_value DMA_TYPE_DEST] == 0} {
 
     add_interface m_dest_axi_clock clock end
     add_interface_port m_dest_axi_clock m_dest_axi_aclk clk Input 1
@@ -241,7 +241,7 @@ proc axi_dmac_elaborate {} {
     add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
   }
 
-  if {[get_parameter_value C_DMA_TYPE_SRC] == 0} {
+  if {[get_parameter_value DMA_TYPE_SRC] == 0} {
 
     add_interface m_src_axi_clock clock end
     add_interface_port m_src_axi_clock m_src_axi_aclk clk Input 1
@@ -257,8 +257,8 @@ proc axi_dmac_elaborate {} {
     add_interface_port m_src_axi m_src_axi_awaddr awaddr Output 32
     add_interface_port m_src_axi m_src_axi_awready awready Input 1
     add_interface_port m_src_axi m_src_axi_wvalid wvalid Output 1
-    add_interface_port m_src_axi m_src_axi_wdata wdata Output C_DMA_DATA_WIDTH_SRC
-    add_interface_port m_src_axi m_src_axi_wstrb wstrb Output C_DMA_DATA_WIDTH_SRC/8
+    add_interface_port m_src_axi m_src_axi_wdata wdata Output DMA_DATA_WIDTH_SRC
+    add_interface_port m_src_axi m_src_axi_wstrb wstrb Output DMA_DATA_WIDTH_SRC/8
     add_interface_port m_src_axi m_src_axi_wready wready Input 1
     add_interface_port m_src_axi m_src_axi_bvalid bvalid Input 1
     add_interface_port m_src_axi m_src_axi_bresp bresp Input 2
@@ -268,7 +268,7 @@ proc axi_dmac_elaborate {} {
     add_interface_port m_src_axi m_src_axi_arready arready Input 1
     add_interface_port m_src_axi m_src_axi_rvalid rvalid Input 1
     add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
-    add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
+    add_interface_port m_src_axi m_src_axi_rdata rdata Input DMA_DATA_WIDTH_SRC
     add_interface_port m_src_axi m_src_axi_rready rready Output 1
     add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
     add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
@@ -285,19 +285,19 @@ proc axi_dmac_elaborate {} {
 
   # axis destination/source
 
-  if {[get_parameter_value C_DMA_TYPE_DEST] == 1} {
+  if {[get_parameter_value DMA_TYPE_DEST] == 1} {
 
     add_interface m_axis_clk clock end
     add_interface_port m_axis_clk m_axis_aclk clk Input 1
- 
+
     add_interface m_axis_if conduit end
     set_interface_property m_axis_if associatedClock m_axis_clk
     add_interface_port m_axis_if m_axis_ready ready Input 1
     add_interface_port m_axis_if m_axis_valid valid Output 1
-    add_interface_port m_axis_if m_axis_data data Output C_DMA_DATA_WIDTH_DEST
+    add_interface_port m_axis_if m_axis_data data Output DMA_DATA_WIDTH_DEST
   }
 
-  if {[get_parameter_value C_DMA_TYPE_SRC] == 1} {
+  if {[get_parameter_value DMA_TYPE_SRC] == 1} {
 
     add_interface s_axis_clk clock end
     add_interface_port s_axis_clk s_axis_aclk clk Input 1
@@ -306,25 +306,25 @@ proc axi_dmac_elaborate {} {
     set_interface_property s_axis_if associatedClock s_axis_clk
     add_interface_port s_axis_if s_axis_ready ready Output 1
     add_interface_port s_axis_if s_axis_valid valid Input 1
-    add_interface_port s_axis_if s_axis_data data Input C_DMA_DATA_WIDTH_SRC
+    add_interface_port s_axis_if s_axis_data data Input DMA_DATA_WIDTH_SRC
     add_interface_port s_axis_if s_axis_user user Input 1
   }
 
   # fifo destination/source
 
-  if {[get_parameter_value C_DMA_TYPE_DEST] == 2} {
+  if {[get_parameter_value DMA_TYPE_DEST] == 2} {
     ad_alt_intf clock   fifo_rd_clk       input   1                       dac_clk
     ad_alt_intf signal  fifo_rd_en        input   1                       dac_valid
     ad_alt_intf signal  fifo_rd_valid     output  1                       dma_valid
-    ad_alt_intf signal  fifo_rd_dout      output  C_DMA_DATA_WIDTH_DEST   dac_data
+    ad_alt_intf signal  fifo_rd_dout      output  DMA_DATA_WIDTH_DEST     dac_data
     ad_alt_intf signal  fifo_rd_underflow output  1                       dac_dunf
     ad_alt_intf signal  fifo_rd_xfer_req  output  1                       dma_xfer_req
   }
 
-  if {[get_parameter_value C_DMA_TYPE_SRC] == 2} {
+  if {[get_parameter_value DMA_TYPE_SRC] == 2} {
     ad_alt_intf clock   fifo_wr_clk       input   1                       adc_clk
     ad_alt_intf signal  fifo_wr_en        input   1                       adc_valid
-    ad_alt_intf signal  fifo_wr_din       input   C_DMA_DATA_WIDTH_SRC    adc_data
+    ad_alt_intf signal  fifo_wr_din       input   DMA_DATA_WIDTH_SRC      adc_data
     ad_alt_intf signal  fifo_wr_overflow  output  1                       adc_dovf
     ad_alt_intf signal  fifo_wr_sync      input   1                       adc_sync
     ad_alt_intf signal  fifo_wr_xfer_req  output  1                       dma_xfer_req
diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl
index a28083b20..1e6f7b92a 100644
--- a/projects/ad6676evb/common/ad6676evb_bd.tcl
+++ b/projects/ad6676evb/common/ad6676evb_bd.tcl
@@ -45,7 +45,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad6676_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad6676_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad6676_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad6676_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad6676_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad6676_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl
index 2d3efdb12..bef712711 100644
--- a/projects/ad9265_fmc/common/ad9265_bd.tcl
+++ b/projects/ad9265_fmc/common/ad9265_bd.tcl
@@ -22,7 +22,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9265_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9265_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9265_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9265_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9265_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9265_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9265_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9265_dma
 
diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl
index eda8d00b1..366db53c4 100644
--- a/projects/ad9434_fmc/common/ad9434_bd.tcl
+++ b/projects/ad9434_fmc/common/ad9434_bd.tcl
@@ -23,7 +23,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9434_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9434_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9434_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9434_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9434_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9434_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}]  $axi_ad9434_dma
 
 # additions to default configuration
diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl
index cf299b1eb..96736f79b 100644
--- a/projects/ad9467_fmc/common/ad9467_bd.tcl
+++ b/projects/ad9467_fmc/common/ad9467_bd.tcl
@@ -22,7 +22,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9467_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9467_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9467_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9467_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9467_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9467_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma
 
diff --git a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl
index c52c6cc19..06f29ca27 100644
--- a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl
+++ b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl
@@ -18,7 +18,7 @@ set axi_ad9739a_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0
 set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9739a_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9739a_dma
 set_property -dict [list CONFIG.FIFO_SIZE {64}] $axi_ad9739a_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9739a_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9739a_dma
 set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9739a_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9739a_dma
 set_property -dict [list CONFIG.AXI_SLICE_SRC {1}]  $axi_ad9739a_dma
diff --git a/projects/cftl_cip/common/cftl_cip_bd.tcl b/projects/cftl_cip/common/cftl_cip_bd.tcl
index 92b48b30b..d5974655c 100644
--- a/projects/cftl_cip/common/cftl_cip_bd.tcl
+++ b/projects/cftl_cip/common/cftl_cip_bd.tcl
@@ -24,7 +24,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $pmod_spi_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $pmod_spi_dma
 set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $pmod_spi_dma
 set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $pmod_spi_dma
-set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $pmod_spi_dma
+set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $pmod_spi_dma
 set_property -dict [list CONFIG.C_CYCLIC {0}] $pmod_spi_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $pmod_spi_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $pmod_spi_dma
diff --git a/projects/cn0363/zed/system_bd.tcl b/projects/cn0363/zed/system_bd.tcl
index fed015c7f..5e70e7717 100644
--- a/projects/cn0363/zed/system_bd.tcl
+++ b/projects/cn0363/zed/system_bd.tcl
@@ -38,7 +38,7 @@ set_property -dict [list \
 		CONFIG.ASYNC_CLK_DEST_REQ 0 \
 		CONFIG.ASYNC_CLK_SRC_DEST 0 \
 		CONFIG.ASYNC_CLK_REQ_SRC 0 \
-		CONFIG.C_2D_TRANSFER 0 \
+		CONFIG.C_DMA_2D_TRANSFER 0 \
 		CONFIG.C_DMA_DATA_WIDTH_SRC 32 \
 		CONFIG.C_DMA_DATA_WIDTH_DEST 64 \
 		CONFIG.C_DMA_AXI_PROTOCOL_DEST 1 \
diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl
index 32a5656f8..1dd1448a8 100644
--- a/projects/daq1/common/daq1_bd.tcl
+++ b/projects/daq1/common/daq1_bd.tcl
@@ -48,7 +48,7 @@ set_property -dict [list CONFIG.ID {1}] [get_bd_cells axi_ad9122_dma]
 set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma]
 set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma]
 set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma]
-set_property -dict [list CONFIG.C_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma]
+set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma]
 set_property -dict [list CONFIG.C_CYCLIC {1}] [get_bd_cells axi_ad9122_dma]
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] [get_bd_cells axi_ad9122_dma]
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_ad9122_dma]
@@ -69,7 +69,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma
 set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma
 set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma
 set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma
-set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_dma
+set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9250_dma
 set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_dma
diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index 1ed7ba212..e3e91e9c5 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -30,7 +30,7 @@ set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
@@ -56,7 +56,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl
index 1b3c4298e..9d21caf14 100644
--- a/projects/daq3/common/daq3_bd.tcl
+++ b/projects/daq3/common/daq3_bd.tcl
@@ -29,7 +29,7 @@ set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9152_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9152_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9152_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9152_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9152_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
@@ -55,7 +55,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl
index be694028a..0caa68488 100644
--- a/projects/fmcadc2/common/fmcadc2_bd.tcl
+++ b/projects/fmcadc2/common/fmcadc2_bd.tcl
@@ -34,7 +34,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9625_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl
index 5ceabe26d..571232b9e 100644
--- a/projects/fmcadc4/common/fmcadc4_bd.tcl
+++ b/projects/fmcadc4/common/fmcadc4_bd.tcl
@@ -44,7 +44,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl
index ad5571565..3fc16ca4b 100644
--- a/projects/fmcadc5/common/fmcadc5_bd.tcl
+++ b/projects/fmcadc5/common/fmcadc5_bd.tcl
@@ -66,7 +66,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9625_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9625_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
index c64390514..1d208d5e0 100644
--- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
+++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
@@ -59,7 +59,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_0_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9250_0_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_0_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_0_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9250_0_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9250_0_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_0_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_0_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_0_dma
@@ -73,7 +73,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_1_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9250_1_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma
diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl
index caca7d537..1c5537bbc 100644
--- a/projects/fmcomms1/common/fmcomms1_bd.tcl
+++ b/projects/fmcomms1/common/fmcomms1_bd.tcl
@@ -31,7 +31,7 @@
   set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma
   set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma
   set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9122_dma
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9122_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma
   set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma
   set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9122_dma
   set_property -dict [list CONFIG.AXI_SLICE_SRC {1}]  $axi_ad9122_dma
@@ -48,7 +48,7 @@
   set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9643_dma
   set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9643_dma
   set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9643_dma
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9643_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9643_dma
   set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9643_dma
   set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9643_dma
   set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9643_dma
diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl
index 4fa14c8ff..c685f1d82 100644
--- a/projects/fmcomms2/common/fmcomms2_bd.tcl
+++ b/projects/fmcomms2/common/fmcomms2_bd.tcl
@@ -37,7 +37,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $axi_ad9361_dac_dma
-set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
 
 set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
@@ -54,7 +54,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_adc_dma
-set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}]  $axi_ad9361_adc_dma
 
 set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]
diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl
index 060306f12..324e5bd12 100644
--- a/projects/fmcomms5/common/fmcomms5_bd.tcl
+++ b/projects/fmcomms5/common/fmcomms5_bd.tcl
@@ -53,7 +53,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_dac_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9361_dac_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_dac_dma
 
@@ -72,7 +72,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_adc_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9361_adc_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
 
diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl
index bfb64a984..829da27fe 100644
--- a/projects/fmcomms6/common/fmcomms6_bd.tcl
+++ b/projects/fmcomms6/common/fmcomms6_bd.tcl
@@ -27,7 +27,7 @@ set axi_ad9652 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9652:1.0 axi
 set axi_ad9652_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9652_dma]
 set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9652_dma
 set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9652_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9652_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9652_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9652_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma
 set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9652_dma
diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl
index e853989e7..ead15bd85 100644
--- a/projects/fmcomms7/common/fmcomms7_bd.tcl
+++ b/projects/fmcomms7/common/fmcomms7_bd.tcl
@@ -65,7 +65,7 @@ set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9144_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma
 set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9144_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9144_dma
@@ -87,7 +87,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma
 set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
-set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma
+set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
 set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
diff --git a/projects/imageon/common/imageon_bd.tcl b/projects/imageon/common/imageon_bd.tcl
index 53da7c749..aa1700c87 100644
--- a/projects/imageon/common/imageon_bd.tcl
+++ b/projects/imageon/common/imageon_bd.tcl
@@ -39,7 +39,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_hdmi_rx_dma
-set_property -dict [list CONFIG.2D_TRANSFER {1}] $axi_hdmi_rx_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {1}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma
diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
index 05426e1e9..24a02c1a9 100644
--- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
+++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
@@ -94,7 +94,7 @@
   set speed_detector_m1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m1_dma]
   set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $speed_detector_m1_dma
   set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $speed_detector_m1_dma
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $speed_detector_m1_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $speed_detector_m1_dma
   set_property -dict [list CONFIG.CYCLIC {0}] $speed_detector_m1_dma
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma
@@ -107,7 +107,7 @@
   set speed_detector_m2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m2_dma]
   set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $speed_detector_m2_dma
   set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $speed_detector_m2_dma
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $speed_detector_m2_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $speed_detector_m2_dma
   set_property -dict [list CONFIG.CYCLIC {0}] $speed_detector_m2_dma
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma
@@ -121,7 +121,7 @@
     # dma motor 1
   set current_monitor_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m1_dma ]
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $current_monitor_m1_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $current_monitor_m1_dma
   set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $current_monitor_m1_dma
   set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $current_monitor_m1_dma
   set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $current_monitor_m1_dma
@@ -139,7 +139,7 @@
     # dma motor 2
   set current_monitor_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m2_dma ]
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $current_monitor_m2_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $current_monitor_m2_dma
   set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $current_monitor_m2_dma
   set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $current_monitor_m2_dma
   set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $current_monitor_m2_dma
@@ -156,7 +156,7 @@
   set controller_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m1 ]
     # dma motor 1
   set controller_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m1_dma ]
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $controller_m1_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $controller_m1_dma
   set_property -dict [list CONFIG.CYCLIC {0}] $controller_m1_dma
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma
     # data packer motor 1
@@ -171,7 +171,7 @@
   set controller_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m2 ]
     # dma motor 2
   set controller_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m2_dma ]
-  set_property -dict [list CONFIG.2D_TRANSFER {0}] $controller_m2_dma
+  set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $controller_m2_dma
   set_property -dict [list CONFIG.CYCLIC {0}] $controller_m2_dma
   set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma
     # data packer motor 2
diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl
index 47654fc27..a073a7b09 100644
--- a/projects/usdrx1/common/usdrx1_bd.tcl
+++ b/projects/usdrx1/common/usdrx1_bd.tcl
@@ -86,7 +86,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_usdrx1_dma
 set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_usdrx1_dma
 set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_usdrx1_dma
 set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma
-set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_usdrx1_dma
+set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_usdrx1_dma
 set_property -dict [list CONFIG.CYCLIC {0}] $axi_usdrx1_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma