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axi_dmac: Change parameter name 2D_TRANSFER 

Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
main
Istvan Csomortani 2015-08-20 10:13:39 +03:00
parent 0ec17fd4d6
commit d52308f074
24 changed files with 134 additions and 134 deletions
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10
library/axi_dmac/axi_dmac.v
View File

@ -178,7 +178,7 @@ parameter ID = 0;
parameter DMA_DATA_WIDTH_SRC = 64;
parameter DMA_DATA_WIDTH_DEST = 64;
parameter DMA_LENGTH_WIDTH = 24;
parameter 2D_TRANSFER = 1;
parameter DMA_DMA_2D_TRANSFER = 1;
parameter ASYNC_CLK_REQ_SRC = 1;
parameter ASYNC_CLK_SRC_DEST = 1;
@ -421,9 +421,9 @@ begin
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
12'h107: up_rdata <= 2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= 2D_TRANSFER ? up_dma_dest_stride : 'h00;
12'h109: up_rdata <= 2D_TRANSFER ? up_dma_src_stride : 'h00;
12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00;
12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00;
12'h10a: up_rdata <= up_transfer_done_bitmap;
12'h10b: up_rdata <= up_transfer_id_eot;
12'h10c: up_rdata <= 'h00; // Status
@ -469,7 +469,7 @@ assign up_sot = up_dma_cyclic ? 1'b0 : up_dma_req_valid & up_dma_req_ready;
assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
generate if (2D_TRANSFER == 1) begin
generate if (DMA_2D_TRANSFER == 1) begin
dmac_2d_transfer #(
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),

158
library/axi_dmac/axi_dmac_hw.tcl
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@ -52,33 +52,33 @@ set_parameter_property ID TYPE INTEGER
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
add_parameter C_DMA_DATA_WIDTH_SRC INTEGER 0
set_parameter_property C_DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
set_parameter_property C_DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC
set_parameter_property C_DMA_DATA_WIDTH_SRC TYPE INTEGER
set_parameter_property C_DMA_DATA_WIDTH_SRC UNITS None
set_parameter_property C_DMA_DATA_WIDTH_SRC HDL_PARAMETER true
add_parameter DMA_DATA_WIDTH_SRC INTEGER 0
set_parameter_property DMA_DATA_WIDTH_SRC DEFAULT_VALUE 64
set_parameter_property DMA_DATA_WIDTH_SRC DISPLAY_NAME C_DMA_DATA_WIDTH_SRC
set_parameter_property DMA_DATA_WIDTH_SRC TYPE INTEGER
set_parameter_property DMA_DATA_WIDTH_SRC UNITS None
set_parameter_property DMA_DATA_WIDTH_SRC HDL_PARAMETER true
add_parameter C_DMA_DATA_WIDTH_DEST INTEGER 0
set_parameter_property C_DMA_DATA_WIDTH_DEST DEFAULT_VALUE 64
set_parameter_property C_DMA_DATA_WIDTH_DEST DISPLAY_NAME C_DMA_DATA_WIDTH_DEST
set_parameter_property C_DMA_DATA_WIDTH_DEST TYPE INTEGER
set_parameter_property C_DMA_DATA_WIDTH_DEST UNITS None
set_parameter_property C_DMA_DATA_WIDTH_DEST HDL_PARAMETER true
add_parameter DMA_DATA_WIDTH_DEST INTEGER 0
set_parameter_property DMA_DATA_WIDTH_DEST DEFAULT_VALUE 64
set_parameter_property DMA_DATA_WIDTH_DEST DISPLAY_NAME C_DMA_DATA_WIDTH_DEST
set_parameter_property DMA_DATA_WIDTH_DEST TYPE INTEGER
set_parameter_property DMA_DATA_WIDTH_DEST UNITS None
set_parameter_property DMA_DATA_WIDTH_DEST HDL_PARAMETER true
add_parameter C_DMA_LENGTH_WIDTH INTEGER 0
set_parameter_property C_DMA_LENGTH_WIDTH DEFAULT_VALUE 14
set_parameter_property C_DMA_LENGTH_WIDTH DISPLAY_NAME C_DMA_LENGTH_WIDTH
set_parameter_property C_DMA_LENGTH_WIDTH TYPE INTEGER
set_parameter_property C_DMA_LENGTH_WIDTH UNITS None
set_parameter_property C_DMA_LENGTH_WIDTH HDL_PARAMETER true
add_parameter DMA_LENGTH_WIDTH INTEGER 0
set_parameter_property DMA_LENGTH_WIDTH DEFAULT_VALUE 14
set_parameter_property DMA_LENGTH_WIDTH DISPLAY_NAME C_DMA_LENGTH_WIDTH
set_parameter_property DMA_LENGTH_WIDTH TYPE INTEGER
set_parameter_property DMA_LENGTH_WIDTH UNITS None
set_parameter_property DMA_LENGTH_WIDTH HDL_PARAMETER true
add_parameter C_2D_TRANSFER INTEGER 0
set_parameter_property C_2D_TRANSFER DEFAULT_VALUE 1
set_parameter_property C_2D_TRANSFER DISPLAY_NAME C_2D_TRANSFER
set_parameter_property C_2D_TRANSFER TYPE INTEGER
set_parameter_property C_2D_TRANSFER UNITS None
set_parameter_property C_2D_TRANSFER HDL_PARAMETER true
add_parameter DMA_2D_TRANSFER INTEGER 0
set_parameter_property DMA_2D_TRANSFER DEFAULT_VALUE 1
set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME C_DMA_2D_TRANSFER
set_parameter_property DMA_2D_TRANSFER TYPE INTEGER
set_parameter_property DMA_2D_TRANSFER UNITS None
set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
add_parameter ASYNC_CLK_REQ_SRC INTEGER 0
set_parameter_property ASYNC_CLK_REQ_SRC DEFAULT_VALUE 1
@ -101,54 +101,54 @@ set_parameter_property ASYNC_CLK_DEST_REQ TYPE INTEGER
set_parameter_property ASYNC_CLK_DEST_REQ UNITS None
set_parameter_property ASYNC_CLK_DEST_REQ HDL_PARAMETER true
add_parameter C_AXI_SLICE_DEST INTEGER 0
set_parameter_property C_AXI_SLICE_DEST DEFAULT_VALUE 0
set_parameter_property C_AXI_SLICE_DEST DISPLAY_NAME C_AXI_SLICE_DEST
set_parameter_property C_AXI_SLICE_DEST TYPE INTEGER
set_parameter_property C_AXI_SLICE_DEST UNITS None
set_parameter_property C_AXI_SLICE_DEST HDL_PARAMETER true
add_parameter AXI_SLICE_DEST INTEGER 0
set_parameter_property AXI_SLICE_DEST DEFAULT_VALUE 0
set_parameter_property AXI_SLICE_DEST DISPLAY_NAME C_AXI_SLICE_DEST
set_parameter_property AXI_SLICE_DEST TYPE INTEGER
set_parameter_property AXI_SLICE_DEST UNITS None
set_parameter_property AXI_SLICE_DEST HDL_PARAMETER true
add_parameter C_AXI_SLICE_SRC INTEGER 0
set_parameter_property C_AXI_SLICE_SRC DEFAULT_VALUE 0
set_parameter_property C_AXI_SLICE_SRC DISPLAY_NAME C_AXI_SLICE_SRC
set_parameter_property C_AXI_SLICE_SRC TYPE INTEGER
set_parameter_property C_AXI_SLICE_SRC UNITS None
set_parameter_property C_AXI_SLICE_SRC HDL_PARAMETER true
add_parameter AXI_SLICE_SRC INTEGER 0
set_parameter_property AXI_SLICE_SRC DEFAULT_VALUE 0
set_parameter_property AXI_SLICE_SRC DISPLAY_NAME C_AXI_SLICE_SRC
set_parameter_property AXI_SLICE_SRC TYPE INTEGER
set_parameter_property AXI_SLICE_SRC UNITS None
set_parameter_property AXI_SLICE_SRC HDL_PARAMETER true
add_parameter C_SYNC_TRANSFER_START INTEGER 0
set_parameter_property C_SYNC_TRANSFER_START DEFAULT_VALUE 0
set_parameter_property C_SYNC_TRANSFER_START DISPLAY_NAME C_SYNC_TRANSFER_START
set_parameter_property C_SYNC_TRANSFER_START TYPE INTEGER
set_parameter_property C_SYNC_TRANSFER_START UNITS None
set_parameter_property C_SYNC_TRANSFER_START HDL_PARAMETER true
add_parameter SYNC_TRANSFER_START INTEGER 0
set_parameter_property SYNC_TRANSFER_START DEFAULT_VALUE 0
set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME C_SYNC_TRANSFER_START
set_parameter_property SYNC_TRANSFER_START TYPE INTEGER
set_parameter_property SYNC_TRANSFER_START UNITS None
set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
add_parameter C_CYCLIC INTEGER 0
set_parameter_property C_CYCLIC DEFAULT_VALUE 1
set_parameter_property C_CYCLIC DISPLAY_NAME C_CYCLIC
set_parameter_property C_CYCLIC TYPE INTEGER
set_parameter_property C_CYCLIC UNITS None
set_parameter_property C_CYCLIC HDL_PARAMETER true
add_parameter CYCLIC INTEGER 0
set_parameter_property CYCLIC DEFAULT_VALUE 1
set_parameter_property CYCLIC DISPLAY_NAME C_CYCLIC
set_parameter_property CYCLIC TYPE INTEGER
set_parameter_property CYCLIC UNITS None
set_parameter_property CYCLIC HDL_PARAMETER true
add_parameter C_DMA_TYPE_DEST INTEGER 0
set_parameter_property C_DMA_TYPE_DEST DEFAULT_VALUE 0
set_parameter_property C_DMA_TYPE_DEST DISPLAY_NAME C_DMA_TYPE_DEST
set_parameter_property C_DMA_TYPE_DEST TYPE INTEGER
set_parameter_property C_DMA_TYPE_DEST UNITS None
set_parameter_property C_DMA_TYPE_DEST HDL_PARAMETER true
add_parameter DMA_TYPE_DEST INTEGER 0
set_parameter_property DMA_TYPE_DEST DEFAULT_VALUE 0
set_parameter_property DMA_TYPE_DEST DISPLAY_NAME C_DMA_TYPE_DEST
set_parameter_property DMA_TYPE_DEST TYPE INTEGER
set_parameter_property DMA_TYPE_DEST UNITS None
set_parameter_property DMA_TYPE_DEST HDL_PARAMETER true
add_parameter C_DMA_TYPE_SRC INTEGER 0
set_parameter_property C_DMA_TYPE_SRC DEFAULT_VALUE 2
set_parameter_property C_DMA_TYPE_SRC DISPLAY_NAME C_DMA_TYPE_SRC
set_parameter_property C_DMA_TYPE_SRC TYPE INTEGER
set_parameter_property C_DMA_TYPE_SRC UNITS None
set_parameter_property C_DMA_TYPE_SRC HDL_PARAMETER true
add_parameter DMA_TYPE_SRC INTEGER 0
set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2
set_parameter_property DMA_TYPE_SRC DISPLAY_NAME C_DMA_TYPE_SRC
set_parameter_property DMA_TYPE_SRC TYPE INTEGER
set_parameter_property DMA_TYPE_SRC UNITS None
set_parameter_property DMA_TYPE_SRC HDL_PARAMETER true
add_parameter C_FIFO_SIZE INTEGER 0 "In bursts"
set_parameter_property C_FIFO_SIZE DEFAULT_VALUE 4
set_parameter_property C_FIFO_SIZE DISPLAY_NAME C_FIFO_SIZE
set_parameter_property C_FIFO_SIZE TYPE INTEGER
set_parameter_property C_FIFO_SIZE UNITS None
set_parameter_property C_FIFO_SIZE HDL_PARAMETER true
add_parameter FIFO_SIZE INTEGER 0 "In bursts"
set_parameter_property FIFO_SIZE DEFAULT_VALUE 4
set_parameter_property FIFO_SIZE DISPLAY_NAME C_FIFO_SIZE
set_parameter_property FIFO_SIZE TYPE INTEGER
set_parameter_property FIFO_SIZE UNITS None
set_parameter_property FIFO_SIZE HDL_PARAMETER true
# axi4 slave
@ -199,7 +199,7 @@ proc axi_dmac_elaborate {} {
# axi4 destination/source
if {[get_parameter_value C_DMA_TYPE_DEST] == 0} {
if {[get_parameter_value DMA_TYPE_DEST] == 0} {
add_interface m_dest_axi_clock clock end
add_interface_port m_dest_axi_clock m_dest_axi_aclk clk Input 1
@ -241,7 +241,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_dest_axi m_dest_axi_arprot arprot Output 3
}
if {[get_parameter_value C_DMA_TYPE_SRC] == 0} {
if {[get_parameter_value DMA_TYPE_SRC] == 0} {
add_interface m_src_axi_clock clock end
add_interface_port m_src_axi_clock m_src_axi_aclk clk Input 1
@ -257,8 +257,8 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_awaddr awaddr Output 32
add_interface_port m_src_axi m_src_axi_awready awready Input 1
add_interface_port m_src_axi m_src_axi_wvalid wvalid Output 1
add_interface_port m_src_axi m_src_axi_wdata wdata Output C_DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_wstrb wstrb Output C_DMA_DATA_WIDTH_SRC/8
add_interface_port m_src_axi m_src_axi_wdata wdata Output DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_wstrb wstrb Output DMA_DATA_WIDTH_SRC/8
add_interface_port m_src_axi m_src_axi_wready wready Input 1
add_interface_port m_src_axi m_src_axi_bvalid bvalid Input 1
add_interface_port m_src_axi m_src_axi_bresp bresp Input 2
@ -268,7 +268,7 @@ proc axi_dmac_elaborate {} {
add_interface_port m_src_axi m_src_axi_arready arready Input 1
add_interface_port m_src_axi m_src_axi_rvalid rvalid Input 1
add_interface_port m_src_axi m_src_axi_rresp rresp Input 2
add_interface_port m_src_axi m_src_axi_rdata rdata Input C_DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_rdata rdata Input DMA_DATA_WIDTH_SRC
add_interface_port m_src_axi m_src_axi_rready rready Output 1
add_interface_port m_src_axi m_src_axi_awlen awlen Output 8
add_interface_port m_src_axi m_src_axi_awsize awsize Output 3
@ -285,7 +285,7 @@ proc axi_dmac_elaborate {} {
# axis destination/source
if {[get_parameter_value C_DMA_TYPE_DEST] == 1} {
if {[get_parameter_value DMA_TYPE_DEST] == 1} {
add_interface m_axis_clk clock end
add_interface_port m_axis_clk m_axis_aclk clk Input 1
@ -294,10 +294,10 @@ proc axi_dmac_elaborate {} {
set_interface_property m_axis_if associatedClock m_axis_clk
add_interface_port m_axis_if m_axis_ready ready Input 1
add_interface_port m_axis_if m_axis_valid valid Output 1
add_interface_port m_axis_if m_axis_data data Output C_DMA_DATA_WIDTH_DEST
add_interface_port m_axis_if m_axis_data data Output DMA_DATA_WIDTH_DEST
}
if {[get_parameter_value C_DMA_TYPE_SRC] == 1} {
if {[get_parameter_value DMA_TYPE_SRC] == 1} {
add_interface s_axis_clk clock end
add_interface_port s_axis_clk s_axis_aclk clk Input 1
@ -306,25 +306,25 @@ proc axi_dmac_elaborate {} {
set_interface_property s_axis_if associatedClock s_axis_clk
add_interface_port s_axis_if s_axis_ready ready Output 1
add_interface_port s_axis_if s_axis_valid valid Input 1
add_interface_port s_axis_if s_axis_data data Input C_DMA_DATA_WIDTH_SRC
add_interface_port s_axis_if s_axis_data data Input DMA_DATA_WIDTH_SRC
add_interface_port s_axis_if s_axis_user user Input 1
}
# fifo destination/source
if {[get_parameter_value C_DMA_TYPE_DEST] == 2} {
if {[get_parameter_value DMA_TYPE_DEST] == 2} {
ad_alt_intf clock fifo_rd_clk input 1 dac_clk
ad_alt_intf signal fifo_rd_en input 1 dac_valid
ad_alt_intf signal fifo_rd_valid output 1 dma_valid
ad_alt_intf signal fifo_rd_dout output C_DMA_DATA_WIDTH_DEST dac_data
ad_alt_intf signal fifo_rd_dout output DMA_DATA_WIDTH_DEST dac_data
ad_alt_intf signal fifo_rd_underflow output 1 dac_dunf
ad_alt_intf signal fifo_rd_xfer_req output 1 dma_xfer_req
}
if {[get_parameter_value C_DMA_TYPE_SRC] == 2} {
if {[get_parameter_value DMA_TYPE_SRC] == 2} {
ad_alt_intf clock fifo_wr_clk input 1 adc_clk
ad_alt_intf signal fifo_wr_en input 1 adc_valid
ad_alt_intf signal fifo_wr_din input C_DMA_DATA_WIDTH_SRC adc_data
ad_alt_intf signal fifo_wr_din input DMA_DATA_WIDTH_SRC adc_data
ad_alt_intf signal fifo_wr_overflow output 1 adc_dovf
ad_alt_intf signal fifo_wr_sync input 1 adc_sync
ad_alt_intf signal fifo_wr_xfer_req output 1 dma_xfer_req

2
projects/ad6676evb/common/ad6676evb_bd.tcl
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@ -45,7 +45,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad6676_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad6676_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma

2
projects/ad9265_fmc/common/ad9265_bd.tcl
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@ -22,7 +22,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9265_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9265_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9265_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9265_dma

2
projects/ad9434_fmc/common/ad9434_bd.tcl
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@ -23,7 +23,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9434_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9434_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9434_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9434_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9434_dma
# additions to default configuration

2
projects/ad9467_fmc/common/ad9467_bd.tcl
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@ -22,7 +22,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9467_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9467_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {16}] $axi_ad9467_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9467_dma

2
projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl
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@ -18,7 +18,7 @@ set axi_ad9739a_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9739a_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9739a_dma
set_property -dict [list CONFIG.FIFO_SIZE {64}] $axi_ad9739a_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9739a_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9739a_dma
set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9739a_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9739a_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9739a_dma

2
projects/cftl_cip/common/cftl_cip_bd.tcl
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@ -24,7 +24,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $pmod_spi_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $pmod_spi_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $pmod_spi_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $pmod_spi_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $pmod_spi_dma
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $pmod_spi_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $pmod_spi_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {16}] $pmod_spi_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $pmod_spi_dma

2
projects/cn0363/zed/system_bd.tcl
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@ -38,7 +38,7 @@ set_property -dict [list \
CONFIG.ASYNC_CLK_DEST_REQ 0 \
CONFIG.ASYNC_CLK_SRC_DEST 0 \
CONFIG.ASYNC_CLK_REQ_SRC 0 \
CONFIG.C_2D_TRANSFER 0 \
CONFIG.C_DMA_2D_TRANSFER 0 \
CONFIG.C_DMA_DATA_WIDTH_SRC 32 \
CONFIG.C_DMA_DATA_WIDTH_DEST 64 \
CONFIG.C_DMA_AXI_PROTOCOL_DEST 1 \

4
projects/daq1/common/daq1_bd.tcl
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@ -48,7 +48,7 @@ set_property -dict [list CONFIG.ID {1}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_CYCLIC {1}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] [get_bd_cells axi_ad9122_dma]
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_ad9122_dma]
@ -69,7 +69,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_dma

4
projects/daq2/common/daq2_bd.tcl
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@ -30,7 +30,7 @@ set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma
@ -56,7 +56,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma

4
projects/daq3/common/daq3_bd.tcl
View File

@ -29,7 +29,7 @@ set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9152_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9152_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9152_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9152_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9152_dma
@ -55,7 +55,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma

2
projects/fmcadc2/common/fmcadc2_bd.tcl
View File

@ -34,7 +34,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma

2
projects/fmcadc4/common/fmcadc4_bd.tcl
View File

@ -44,7 +44,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma

2
projects/fmcadc5/common/fmcadc5_bd.tcl
View File

@ -66,7 +66,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9625_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9625_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma

4
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
View File

@ -59,7 +59,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_0_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_0_dma
@ -73,7 +73,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_1_dma

4
projects/fmcomms1/common/fmcomms1_bd.tcl
View File

@ -31,7 +31,7 @@
set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma
set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9122_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9122_dma
@ -48,7 +48,7 @@
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9643_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.FIFO_SIZE {16}] $axi_ad9643_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9643_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9643_dma

4
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -37,7 +37,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma
set util_ad9361_dac_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9361_dac_upack]
@ -54,7 +54,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma
set util_ad9361_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9361_adc_pack]

4
projects/fmcomms5/common/fmcomms5_bd.tcl
View File

@ -53,7 +53,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_dac_dma
@ -72,7 +72,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma

2
projects/fmcomms6/common/fmcomms6_bd.tcl
View File

@ -27,7 +27,7 @@ set axi_ad9652 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9652:1.0 axi
set axi_ad9652_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9652_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9652_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9652_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9652_dma
set_property -dict [list CONFIG.FIFO_SIZE {8}] $axi_ad9652_dma

4
projects/fmcomms7/common/fmcomms7_bd.tcl
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@ -65,7 +65,7 @@ set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9144_dma
set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $axi_ad9144_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {256}] $axi_ad9144_dma
@ -87,7 +87,7 @@ set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma

2
projects/imageon/common/imageon_bd.tcl
View File

@ -39,7 +39,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.2D_TRANSFER {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {14}] $axi_hdmi_rx_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_hdmi_rx_dma

12
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
View File

@ -94,7 +94,7 @@
set speed_detector_m1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m1_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $speed_detector_m1_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.CYCLIC {0}] $speed_detector_m1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma
@ -107,7 +107,7 @@
set speed_detector_m2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m2_dma]
set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $speed_detector_m2_dma
set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.CYCLIC {0}] $speed_detector_m2_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma
@ -121,7 +121,7 @@
# dma motor 1
set current_monitor_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m1_dma ]
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $current_monitor_m1_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $current_monitor_m1_dma
@ -139,7 +139,7 @@
# dma motor 2
set current_monitor_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m2_dma ]
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {0}] $current_monitor_m2_dma
set_property -dict [list CONFIG.ASYNC_CLK_SRC_DEST {0}] $current_monitor_m2_dma
@ -156,7 +156,7 @@
set controller_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m1 ]
# dma motor 1
set controller_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m1_dma ]
set_property -dict [list CONFIG.2D_TRANSFER {0}] $controller_m1_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $controller_m1_dma
set_property -dict [list CONFIG.CYCLIC {0}] $controller_m1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma
# data packer motor 1
@ -171,7 +171,7 @@
set controller_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m2 ]
# dma motor 2
set controller_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m2_dma ]
set_property -dict [list CONFIG.2D_TRANSFER {0}] $controller_m2_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $controller_m2_dma
set_property -dict [list CONFIG.CYCLIC {0}] $controller_m2_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma
# data packer motor 2

2
projects/usdrx1/common/usdrx1_bd.tcl
View File

@ -86,7 +86,7 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.ASYNC_CLK_DEST_REQ {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma
set_property -dict [list CONFIG.2D_TRANSFER {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.CYCLIC {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma