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adrv9009/intel: Fix fPLL configuration 

When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
main
Istvan Csomortani 2021-01-05 09:00:10 +00:00 committed by István Csomortáni
parent b8d294cdd9
commit d539a8119c
3 changed files with 14 additions and 10 deletions
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4
projects/adrv9009/a10gx/system_constr.sdc
View File

@ -1,7 +1,7 @@
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.069 ns" -name ref_clk0 [get_ports {ref_clk0}]
create_clock -period "4.069 ns" -name ref_clk1 [get_ports {ref_clk1}]
create_clock -period "4.06504065 ns" -name ref_clk0 [get_ports {ref_clk0}]
create_clock -period "4.06504065 ns" -name ref_clk1 [get_ports {ref_clk1}]
derive_pll_clocks
derive_clock_uncertainty

4
projects/adrv9009/a10soc/system_constr.sdc
View File

@ -1,7 +1,7 @@
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "4.069 ns" -name ref_clk0 [get_ports {ref_clk0}]
create_clock -period "4.069 ns" -name ref_clk1 [get_ports {ref_clk1}]
create_clock -period "4.06504065 ns" -name ref_clk0 [get_ports {ref_clk0}]
create_clock -period "4.06504065 ns" -name ref_clk1 [get_ports {ref_clk1}]
derive_pll_clocks
derive_clock_uncertainty

16
projects/adrv9009/common/adrv9009_qsys.tcl
View File

@ -27,14 +27,18 @@ set dac_fifo_name avl_adrv9009_tx_fifo
set dac_data_width 128
set dac_dma_data_width 128
# NOTE: The real lane rate is 2457.6 Gbps (Tx) and 4915.2 Gbps (RX/Rx_Obs),
# with a real reference clock frequency of 122.88 MHz. A round up needed
# because the fPLL's configuration interface does not support fractional numbers.
# adrv9009_tx JESD204
add_instance adrv9009_tx_jesd204 adi_jesd204
set_instance_parameter_value adrv9009_tx_jesd204 {ID} {0}
set_instance_parameter_value adrv9009_tx_jesd204 {TX_OR_RX_N} {1}
set_instance_parameter_value adrv9009_tx_jesd204 {SOFT_PCS} {true}
set_instance_parameter_value adrv9009_tx_jesd204 {LANE_RATE} {2457.6}
set_instance_parameter_value adrv9009_tx_jesd204 {REFCLK_FREQUENCY} {122.88}
set_instance_parameter_value adrv9009_tx_jesd204 {LANE_RATE} {2460}
set_instance_parameter_value adrv9009_tx_jesd204 {REFCLK_FREQUENCY} {123}
set_instance_parameter_value adrv9009_tx_jesd204 {NUM_OF_LANES} $TX_NUM_OF_LANES
set_instance_parameter_value adrv9009_tx_jesd204 {LANE_MAP} {0 3 2 1}
@ -55,8 +59,8 @@ add_instance adrv9009_rx_jesd204 adi_jesd204
set_instance_parameter_value adrv9009_rx_jesd204 {ID} {1}
set_instance_parameter_value adrv9009_rx_jesd204 {TX_OR_RX_N} {0}
set_instance_parameter_value adrv9009_rx_jesd204 {SOFT_PCS} {true}
set_instance_parameter_value adrv9009_rx_jesd204 {LANE_RATE} {4915.2}
set_instance_parameter_value adrv9009_rx_jesd204 {REFCLK_FREQUENCY} {122.88}
set_instance_parameter_value adrv9009_rx_jesd204 {LANE_RATE} {4920}
set_instance_parameter_value adrv9009_rx_jesd204 {REFCLK_FREQUENCY} {123}
set_instance_parameter_value adrv9009_rx_jesd204 {NUM_OF_LANES} $RX_NUM_OF_LANES
set_instance_parameter_value adrv9009_rx_jesd204 {INPUT_PIPELINE_STAGES} {1}
@ -77,8 +81,8 @@ add_instance adrv9009_rx_os_jesd204 adi_jesd204
set_instance_parameter_value adrv9009_rx_os_jesd204 {ID} {1}
set_instance_parameter_value adrv9009_rx_os_jesd204 {TX_OR_RX_N} {0}
set_instance_parameter_value adrv9009_rx_os_jesd204 {SOFT_PCS} {true}
set_instance_parameter_value adrv9009_rx_os_jesd204 {LANE_RATE} {4915.2}
set_instance_parameter_value adrv9009_rx_os_jesd204 {REFCLK_FREQUENCY} {122.88}
set_instance_parameter_value adrv9009_rx_os_jesd204 {LANE_RATE} {4920}
set_instance_parameter_value adrv9009_rx_os_jesd204 {REFCLK_FREQUENCY} {123}
set_instance_parameter_value adrv9009_rx_os_jesd204 {NUM_OF_LANES} $RX_OS_NUM_OF_LANES
set_instance_parameter_value adrv9009_rx_os_jesd204 {INPUT_PIPELINE_STAGES} {1}