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Merge branch 'dev' into hdl_2016_r2

main
Istvan Csomortani 2017-01-30 17:10:05 +02:00
parent 746b97dd96 db924953bb
commit d5af828b9c
53 changed files with 1471 additions and 644 deletions
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4
library/altera/avl_adxcfg/avl_adxcfg.v
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@ -80,8 +80,8 @@ module avl_adxcfg (
reg [ 9:0] rcfg_address_int = 'd0; reg [ 9:0] rcfg_address_int = 'd0;
reg [31:0] rcfg_writedata_int = 'd0; reg [31:0] rcfg_writedata_int = 'd0;
reg [31:0] rcfg_readdata_int = 'd0; reg [31:0] rcfg_readdata_int = 'd0;
reg rcfg_waitrequest_int_0 = 'd0; reg rcfg_waitrequest_int_0 = 'd1;
reg rcfg_waitrequest_int_1 = 'd0; reg rcfg_waitrequest_int_1 = 'd1;
// internal signals // internal signals

438
library/axi_ad9152/axi_ad9152_channel.v
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@ -34,8 +34,6 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
@ -104,8 +102,6 @@ module axi_ad9152_channel (
reg [63:0] dac_data = 'd0; reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0; reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0; reg [63:0] dac_pn15_data = 'd0;
reg [63:0] dac_pn23_data = 'd0;
reg [63:0] dac_pn31_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0; reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0; reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0; reg [15:0] dac_dds_phase_1_0 = 'd0;
@ -133,312 +129,174 @@ module axi_ad9152_channel (
wire [15:0] dac_pat_data_1_s; wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s; wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s; wire [ 3:0] dac_data_sel_s;
wire [63:0] dac_pn7_data_i_s;
wire [63:0] dac_pn15_data_i_s;
wire [63:0] dac_pn7_data_s;
wire [63:0] dac_pn15_data_s;
// pn7 function // PN7 function
function [63:0] pn7; function [63:0] pn7;
input [63:0] din; input [7:0] din;
reg [63:0] dout; reg [63:0] dout;
begin begin
dout[63] = din[ 7] ^ din[ 6]; dout[15] = din[ 6] ^ din[ 5];
dout[62] = din[ 6] ^ din[ 5]; dout[14] = din[ 5] ^ din[ 4];
dout[61] = din[ 5] ^ din[ 4]; dout[13] = din[ 4] ^ din[ 3];
dout[60] = din[ 4] ^ din[ 3]; dout[12] = din[ 3] ^ din[ 2];
dout[59] = din[ 3] ^ din[ 2]; dout[11] = din[ 2] ^ din[ 1];
dout[58] = din[ 2] ^ din[ 1]; dout[10] = din[ 1] ^ din[ 0];
dout[57] = din[ 1] ^ din[ 0]; dout[ 9] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[56] = din[ 0] ^ din[ 7] ^ din[ 6]; dout[ 8] = din[ 6] ^ din[ 4];
dout[55] = din[ 7] ^ din[ 5]; dout[ 7] = din[ 5] ^ din[ 3];
dout[54] = din[ 6] ^ din[ 4]; dout[ 6] = din[ 4] ^ din[ 2];
dout[53] = din[ 5] ^ din[ 3]; dout[ 5] = din[ 3] ^ din[ 1];
dout[52] = din[ 4] ^ din[ 2]; dout[ 4] = din[ 2] ^ din[ 0];
dout[51] = din[ 3] ^ din[ 1]; dout[ 3] = din[ 1] ^ din[ 6] ^ din[ 5];
dout[50] = din[ 2] ^ din[ 0]; dout[ 2] = din[ 0] ^ din[ 5] ^ din[ 4];
dout[49] = din[ 1] ^ din[ 7] ^ din[ 6]; dout[ 1] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[48] = din[ 0] ^ din[ 6] ^ din[ 5]; dout[ 0] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; dout[31] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; dout[30] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; dout[29] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 5];
dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; dout[28] = din[ 1] ^ din[ 6] ^ din[ 0] ^ din[ 4];
dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; dout[27] = din[ 0] ^ din[ 6] ^ din[ 3];
dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6]; dout[26] = din[ 6] ^ din[ 2];
dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5]; dout[25] = din[ 5] ^ din[ 1];
dout[40] = din[ 0] ^ din[ 7] ^ din[ 4]; dout[24] = din[ 4] ^ din[ 0];
dout[39] = din[ 7] ^ din[ 3]; dout[23] = din[ 3] ^ din[ 6] ^ din[ 5];
dout[38] = din[ 6] ^ din[ 2]; dout[22] = din[ 2] ^ din[ 5] ^ din[ 4];
dout[37] = din[ 5] ^ din[ 1]; dout[21] = din[ 1] ^ din[ 4] ^ din[ 3];
dout[36] = din[ 4] ^ din[ 0]; dout[20] = din[ 0] ^ din[ 3] ^ din[ 2];
dout[35] = din[ 3] ^ din[ 7] ^ din[ 6]; dout[19] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[34] = din[ 2] ^ din[ 6] ^ din[ 5]; dout[18] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[33] = din[ 1] ^ din[ 5] ^ din[ 4]; dout[17] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[32] = din[ 0] ^ din[ 4] ^ din[ 3]; dout[16] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 4];
dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2]; dout[47] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 3];
dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; dout[46] = din[ 1] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0]; dout[45] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 1];
dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6]; dout[44] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5]; dout[43] = din[ 1] ^ din[ 3] ^ din[ 6];
dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4]; dout[42] = din[ 0] ^ din[ 5] ^ din[ 2];
dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3]; dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 0];
dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1]; dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 6] ^ din[ 5];
dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; dout[38] = din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 2] ^ din[ 4];
dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6]; dout[37] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 1] ^ din[ 3];
dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5]; dout[36] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 5] ^ din[ 2];
dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4]; dout[35] = din[ 0] ^ din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 1];
dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3]; dout[34] = din[ 6] ^ din[ 1] ^ din[ 3] ^ din[ 0];
dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2]; dout[33] = din[ 0] ^ din[ 2] ^ din[ 6];
dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1]; dout[32] = din[ 6] ^ din[ 1];
dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0]; dout[63] = din[ 5] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7]; dout[62] = din[ 4] ^ din[ 6] ^ din[ 5];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2]; dout[61] = din[ 3] ^ din[ 5] ^ din[ 4];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1]; dout[60] = din[ 2] ^ din[ 4] ^ din[ 3];
dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0]; dout[59] = din[ 1] ^ din[ 3] ^ din[ 2];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 7]; dout[58] = din[ 0] ^ din[ 2] ^ din[ 1];
dout[ 9] = din[ 7] ^ din[ 0]; dout[57] = din[ 6] ^ din[ 1] ^ din[ 5] ^ din[ 0];
dout[ 8] = din[ 7]; dout[56] = din[ 0] ^ din[ 4] ^ din[ 6];
dout[ 7] = din[ 6]; dout[55] = din[ 6] ^ din[ 3];
dout[ 6] = din[ 5]; dout[54] = din[ 5] ^ din[ 2];
dout[ 5] = din[ 4]; dout[53] = din[ 4] ^ din[ 1];
dout[ 4] = din[ 3]; dout[52] = din[ 3] ^ din[ 0];
dout[ 3] = din[ 2]; dout[51] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[ 2] = din[ 1]; dout[50] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[ 1] = din[ 0]; dout[49] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[ 0] = din[ 7] ^ din[ 6]; dout[48] = din[ 6] ^ din[ 3] ^ din[ 5] ^ din[ 2];
pn7 = dout; pn7 = dout;
end end
endfunction endfunction
// pn15 function // PN15 function
function [63:0] pn15; function [63:0] pn15;
input [63:0] din; input [15:0] din;
reg [63:0] dout; reg [63:0] dout;
begin begin
dout[63] = din[15] ^ din[14]; dout[15] = din[14] ^ din[13];
dout[62] = din[14] ^ din[13]; dout[14] = din[13] ^ din[12];
dout[61] = din[13] ^ din[12]; dout[13] = din[12] ^ din[11];
dout[60] = din[12] ^ din[11]; dout[12] = din[11] ^ din[10];
dout[59] = din[11] ^ din[10]; dout[11] = din[10] ^ din[ 9];
dout[58] = din[10] ^ din[ 9]; dout[10] = din[ 9] ^ din[ 8];
dout[57] = din[ 9] ^ din[ 8]; dout[ 9] = din[ 8] ^ din[ 7];
dout[56] = din[ 8] ^ din[ 7]; dout[ 8] = din[ 7] ^ din[ 6];
dout[55] = din[ 7] ^ din[ 6]; dout[ 7] = din[ 6] ^ din[ 5];
dout[54] = din[ 6] ^ din[ 5]; dout[ 6] = din[ 5] ^ din[ 4];
dout[53] = din[ 5] ^ din[ 4]; dout[ 5] = din[ 4] ^ din[ 3];
dout[52] = din[ 4] ^ din[ 3]; dout[ 4] = din[ 3] ^ din[ 2];
dout[51] = din[ 3] ^ din[ 2]; dout[ 3] = din[ 2] ^ din[ 1];
dout[50] = din[ 2] ^ din[ 1]; dout[ 2] = din[ 1] ^ din[ 0];
dout[49] = din[ 1] ^ din[ 0]; dout[ 1] = din[ 0] ^ din[14] ^ din[13];
dout[48] = din[ 0] ^ din[15] ^ din[14]; dout[ 0] = din[14] ^ din[12];
dout[47] = din[15] ^ din[13]; dout[31] = din[13] ^ din[11];
dout[46] = din[14] ^ din[12]; dout[30] = din[12] ^ din[10];
dout[45] = din[13] ^ din[11]; dout[29] = din[11] ^ din[ 9];
dout[44] = din[12] ^ din[10]; dout[28] = din[10] ^ din[ 8];
dout[43] = din[11] ^ din[ 9]; dout[27] = din[ 9] ^ din[ 7];
dout[42] = din[10] ^ din[ 8]; dout[26] = din[ 8] ^ din[ 6];
dout[41] = din[ 9] ^ din[ 7]; dout[25] = din[ 7] ^ din[ 5];
dout[40] = din[ 8] ^ din[ 6]; dout[24] = din[ 6] ^ din[ 4];
dout[39] = din[ 7] ^ din[ 5]; dout[23] = din[ 5] ^ din[ 3];
dout[38] = din[ 6] ^ din[ 4]; dout[22] = din[ 4] ^ din[ 2];
dout[37] = din[ 5] ^ din[ 3]; dout[21] = din[ 3] ^ din[ 1];
dout[36] = din[ 4] ^ din[ 2]; dout[20] = din[ 2] ^ din[ 0];
dout[35] = din[ 3] ^ din[ 1]; dout[19] = din[ 1] ^ din[14] ^ din[13];
dout[34] = din[ 2] ^ din[ 0]; dout[18] = din[ 0] ^ din[13] ^ din[12];
dout[33] = din[ 1] ^ din[15] ^ din[14]; dout[17] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[32] = din[ 0] ^ din[14] ^ din[13]; dout[16] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12]; dout[47] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11]; dout[46] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10]; dout[45] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9]; dout[44] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8]; dout[43] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7]; dout[42] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6]; dout[41] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5]; dout[40] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4]; dout[39] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3]; dout[38] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2]; dout[37] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[14] ^ din[13];
dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1]; dout[36] = din[ 1] ^ din[14] ^ din[ 0] ^ din[12];
dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0]; dout[35] = din[ 0] ^ din[14] ^ din[11];
dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14]; dout[34] = din[14] ^ din[10];
dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13]; dout[33] = din[13] ^ din[ 9];
dout[16] = din[ 0] ^ din[15] ^ din[12]; dout[32] = din[12] ^ din[ 8];
dout[15] = din[15] ^ din[11]; dout[63] = din[11] ^ din[ 7];
dout[14] = din[14] ^ din[10]; dout[62] = din[10] ^ din[ 6];
dout[13] = din[13] ^ din[ 9]; dout[61] = din[ 9] ^ din[ 5];
dout[12] = din[12] ^ din[ 8]; dout[60] = din[ 8] ^ din[ 4];
dout[11] = din[11] ^ din[ 7]; dout[59] = din[ 7] ^ din[ 3];
dout[10] = din[10] ^ din[ 6]; dout[58] = din[ 6] ^ din[ 2];
dout[ 9] = din[ 9] ^ din[ 5]; dout[57] = din[ 5] ^ din[ 1];
dout[ 8] = din[ 8] ^ din[ 4]; dout[56] = din[ 4] ^ din[ 0];
dout[ 7] = din[ 7] ^ din[ 3]; dout[55] = din[ 3] ^ din[14] ^ din[13];
dout[ 6] = din[ 6] ^ din[ 2]; dout[54] = din[ 2] ^ din[13] ^ din[12];
dout[ 5] = din[ 5] ^ din[ 1]; dout[53] = din[ 1] ^ din[12] ^ din[11];
dout[ 4] = din[ 4] ^ din[ 0]; dout[52] = din[ 0] ^ din[11] ^ din[10];
dout[ 3] = din[ 3] ^ din[15] ^ din[14]; dout[51] = din[14] ^ din[10] ^ din[13] ^ din[ 9];
dout[ 2] = din[ 2] ^ din[14] ^ din[13]; dout[50] = din[13] ^ din[ 9] ^ din[12] ^ din[ 8];
dout[ 1] = din[ 1] ^ din[13] ^ din[12]; dout[49] = din[12] ^ din[ 8] ^ din[11] ^ din[ 7];
dout[ 0] = din[ 0] ^ din[12] ^ din[11]; dout[48] = din[11] ^ din[ 7] ^ din[10] ^ din[ 6];
pn15 = dout; pn15 = dout;
end end
endfunction endfunction
// pn23 function assign dac_pn7_data_i_s = ~dac_pn7_data;
assign dac_pn15_data_i_s = ~dac_pn15_data;
function [63:0] pn23; assign dac_pn7_data_s = dac_pn7_data;
input [63:0] din; assign dac_pn15_data_s = dac_pn15_data;
reg [63:0] dout;
begin
dout[63] = din[23] ^ din[18];
dout[62] = din[22] ^ din[17];
dout[61] = din[21] ^ din[16];
dout[60] = din[20] ^ din[15];
dout[59] = din[19] ^ din[14];
dout[58] = din[18] ^ din[13];
dout[57] = din[17] ^ din[12];
dout[56] = din[16] ^ din[11];
dout[55] = din[15] ^ din[10];
dout[54] = din[14] ^ din[ 9];
dout[53] = din[13] ^ din[ 8];
dout[52] = din[12] ^ din[ 7];
dout[51] = din[11] ^ din[ 6];
dout[50] = din[10] ^ din[ 5];
dout[49] = din[ 9] ^ din[ 4];
dout[48] = din[ 8] ^ din[ 3];
dout[47] = din[ 7] ^ din[ 2];
dout[46] = din[ 6] ^ din[ 1];
dout[45] = din[ 5] ^ din[ 0];
dout[44] = din[ 4] ^ din[23] ^ din[18];
dout[43] = din[ 3] ^ din[22] ^ din[17];
dout[42] = din[ 2] ^ din[21] ^ din[16];
dout[41] = din[ 1] ^ din[20] ^ din[15];
dout[40] = din[ 0] ^ din[19] ^ din[14];
dout[39] = din[23] ^ din[13];
dout[38] = din[22] ^ din[12];
dout[37] = din[21] ^ din[11];
dout[36] = din[20] ^ din[10];
dout[35] = din[19] ^ din[ 9];
dout[34] = din[18] ^ din[ 8];
dout[33] = din[17] ^ din[ 7];
dout[32] = din[16] ^ din[ 6];
dout[31] = din[15] ^ din[ 5];
dout[30] = din[14] ^ din[ 4];
dout[29] = din[13] ^ din[ 3];
dout[28] = din[12] ^ din[ 2];
dout[27] = din[11] ^ din[ 1];
dout[26] = din[10] ^ din[ 0];
dout[25] = din[ 9] ^ din[23] ^ din[18];
dout[24] = din[ 8] ^ din[22] ^ din[17];
dout[23] = din[ 7] ^ din[21] ^ din[16];
dout[22] = din[ 6] ^ din[20] ^ din[15];
dout[21] = din[ 5] ^ din[19] ^ din[14];
dout[20] = din[ 4] ^ din[18] ^ din[13];
dout[19] = din[ 3] ^ din[17] ^ din[12];
dout[18] = din[ 2] ^ din[16] ^ din[11];
dout[17] = din[ 1] ^ din[15] ^ din[10];
dout[16] = din[ 0] ^ din[14] ^ din[ 9];
dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
pn23 = dout;
end
endfunction
// pn31 function
function [63:0] pn31;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[31] ^ din[28];
dout[62] = din[30] ^ din[27];
dout[61] = din[29] ^ din[26];
dout[60] = din[28] ^ din[25];
dout[59] = din[27] ^ din[24];
dout[58] = din[26] ^ din[23];
dout[57] = din[25] ^ din[22];
dout[56] = din[24] ^ din[21];
dout[55] = din[23] ^ din[20];
dout[54] = din[22] ^ din[19];
dout[53] = din[21] ^ din[18];
dout[52] = din[20] ^ din[17];
dout[51] = din[19] ^ din[16];
dout[50] = din[18] ^ din[15];
dout[49] = din[17] ^ din[14];
dout[48] = din[16] ^ din[13];
dout[47] = din[15] ^ din[12];
dout[46] = din[14] ^ din[11];
dout[45] = din[13] ^ din[10];
dout[44] = din[12] ^ din[ 9];
dout[43] = din[11] ^ din[ 8];
dout[42] = din[10] ^ din[ 7];
dout[41] = din[ 9] ^ din[ 6];
dout[40] = din[ 8] ^ din[ 5];
dout[39] = din[ 7] ^ din[ 4];
dout[38] = din[ 6] ^ din[ 3];
dout[37] = din[ 5] ^ din[ 2];
dout[36] = din[ 4] ^ din[ 1];
dout[35] = din[ 3] ^ din[ 0];
dout[34] = din[ 2] ^ din[31] ^ din[28];
dout[33] = din[ 1] ^ din[30] ^ din[27];
dout[32] = din[ 0] ^ din[29] ^ din[26];
dout[31] = din[31] ^ din[25];
dout[30] = din[30] ^ din[24];
dout[29] = din[29] ^ din[23];
dout[28] = din[28] ^ din[22];
dout[27] = din[27] ^ din[21];
dout[26] = din[26] ^ din[20];
dout[25] = din[25] ^ din[19];
dout[24] = din[24] ^ din[18];
dout[23] = din[23] ^ din[17];
dout[22] = din[22] ^ din[16];
dout[21] = din[21] ^ din[15];
dout[20] = din[20] ^ din[14];
dout[19] = din[19] ^ din[13];
dout[18] = din[18] ^ din[12];
dout[17] = din[17] ^ din[11];
dout[16] = din[16] ^ din[10];
dout[15] = din[15] ^ din[ 9];
dout[14] = din[14] ^ din[ 8];
dout[13] = din[13] ^ din[ 7];
dout[12] = din[12] ^ din[ 6];
dout[11] = din[11] ^ din[ 5];
dout[10] = din[10] ^ din[ 4];
dout[ 9] = din[ 9] ^ din[ 3];
dout[ 8] = din[ 8] ^ din[ 2];
dout[ 7] = din[ 7] ^ din[ 1];
dout[ 6] = din[ 6] ^ din[ 0];
dout[ 5] = din[ 5] ^ din[31] ^ din[28];
dout[ 4] = din[ 4] ^ din[30] ^ din[27];
dout[ 3] = din[ 3] ^ din[29] ^ din[26];
dout[ 2] = din[ 2] ^ din[28] ^ din[25];
dout[ 1] = din[ 1] ^ din[27] ^ din[24];
dout[ 0] = din[ 0] ^ din[26] ^ din[23];
pn31 = dout;
end
endfunction
// dac data select // dac data select
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s) case (dac_data_sel_s)
4'h7: dac_data <= dac_pn31_data; 4'h7: dac_data <= dac_pn15_data_s;
4'h6: dac_data <= dac_pn23_data; 4'h6: dac_data <= dac_pn7_data_s;
4'h5: dac_data <= dac_pn15_data; 4'h5: dac_data <= dac_pn15_data_i_s;
4'h4: dac_data <= dac_pn7_data; 4'h4: dac_data <= dac_pn7_data_i_s;
4'h3: dac_data <= 64'd0; 4'h3: dac_data <= 64'd0;
4'h2: dac_data <= dma_data; 4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s, 4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
@ -453,13 +311,9 @@ module axi_ad9152_channel (
if (dac_data_sync == 1'b1) begin if (dac_data_sync == 1'b1) begin
dac_pn7_data <= {64{1'd1}}; dac_pn7_data <= {64{1'd1}};
dac_pn15_data <= {64{1'd1}}; dac_pn15_data <= {64{1'd1}};
dac_pn23_data <= {64{1'd1}};
dac_pn31_data <= {64{1'd1}};
end else begin end else begin
dac_pn7_data <= pn7(dac_pn7_data); dac_pn7_data <= pn7(dac_pn7_data[55:48]);
dac_pn15_data <= pn15(dac_pn15_data); dac_pn15_data <= pn15(dac_pn15_data[63:48]);
dac_pn23_data <= pn23(dac_pn23_data);
dac_pn31_data <= pn31(dac_pn31_data);
end end
end end

1
library/axi_dmac/axi_dmac.v
View File

@ -420,6 +420,7 @@ begin
12'h000: up_rdata <= PCORE_VERSION; 12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID; 12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch; 12'h002: up_rdata <= up_scratch;
12'h003: up_rdata <= 32'h444d4143; // "DMAC"
12'h020: up_rdata <= up_irq_mask; 12'h020: up_rdata <= up_irq_mask;
12'h021: up_rdata <= up_irq_pending; 12'h021: up_rdata <= up_irq_pending;
12'h022: up_rdata <= up_irq_source; 12'h022: up_rdata <= up_irq_source;

3
library/axi_dmac/axi_dmac_ip.tcl
View File

@ -36,6 +36,9 @@ adi_ip_add_core_dependencies { \
analog.com:user:util_axis_fifo:1.0 \ analog.com:user:util_axis_fifo:1.0 \
} }
set_property display_name "ADI AXI DMA Controller" [ipx::current_core]
set_property description "ADI AXI DMA Controller" [ipx::current_core]
adi_add_bus "s_axis" "slave" \ adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \

11
library/common/ad_mem.v
View File

@ -1,9 +1,9 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc. // Copyright 2011(c) Analog Devices, Inc.
// //
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without modification, // Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met: // are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright // - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software. // patent holders to use this software.
// - Use of the software either in source or binary form, must be run // - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component. // on or directly connected to an Analog Devices Inc. component.
// //
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. // PARTICULAR PURPOSE ARE DISCLAIMED.
// //
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
@ -64,6 +64,7 @@ module ad_mem (
input [AW:0] addrb; input [AW:0] addrb;
output [DW:0] doutb; output [DW:0] doutb;
(* ram_style = "block" *)
reg [DW:0] m_ram[0:((2**ADDRESS_WIDTH)-1)]; reg [DW:0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
reg [DW:0] doutb; reg [DW:0] doutb;

4
library/common/up_dac_common.v
View File

@ -104,8 +104,8 @@ module up_dac_common #(
// internal registers // internal registers
reg up_core_preset = 'd0; reg up_core_preset = 'd1;
reg up_mmcm_preset = 'd0; reg up_mmcm_preset = 'd1;
reg up_wack_int = 'd0; reg up_wack_int = 'd0;
reg [31:0] up_scratch = 'd0; reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0; reg up_mmcm_resetn = 'd0;

1
library/util_clkdiv/Makefile
View File

@ -8,6 +8,7 @@
M_DEPS += ../scripts/adi_env.tcl M_DEPS += ../scripts/adi_env.tcl
M_DEPS += ../scripts/adi_ip.tcl M_DEPS += ../scripts/adi_ip.tcl
M_DEPS += util_clkdiv.v M_DEPS += util_clkdiv.v
M_DEPS += util_clkdiv_constr.xdc
M_DEPS += util_clkdiv_ip.tcl M_DEPS += util_clkdiv_ip.tcl
M_VIVADO := vivado -mode batch -source M_VIVADO := vivado -mode batch -source

53
library/util_clkdiv/util_clkdiv.v
View File

@ -34,8 +34,9 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1 using // Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if
// BUFR and BUFGMUX primitives // clk_sel is 1. Provides a glitch free output clock
// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
@ -47,30 +48,56 @@ module util_clkdiv (
output clk_out output clk_out
); );
wire clk_div_2_s; parameter SIM_DEVICE = "7SERIES";
wire clk_div_4_s; parameter SEL_0_DIV = "4";
parameter SEL_1_DIV = "2";
wire clk_div_sel_0_s;
wire clk_div_sel_1_s;
generate if (SIM_DEVICE == "7SERIES") begin
BUFR #( BUFR #(
.BUFR_DIVIDE("2"), .BUFR_DIVIDE(SEL_0_DIV),
.SIM_DEVICE("7SERIES") .SIM_DEVICE("7SERIES")
) clk_divide_2 ( ) clk_divide_sel_0 (
.I(clk), .I(clk),
.CE(1), .CE(1),
.CLR(0), .CLR(0),
.O(clk_div_2_s)); .O(clk_div_sel_0_s));
BUFR #( BUFR #(
.BUFR_DIVIDE("4"), .BUFR_DIVIDE(SEL_1_DIV),
.SIM_DEVICE("7SERIES") .SIM_DEVICE("7SERIES")
) clk_divide_4 ( ) clk_divide_sel_1 (
.I(clk), .I(clk),
.CE(1), .CE(1),
.CLR(0), .CLR(0),
.O(clk_div_4_s)); .O(clk_div_sel_1_s));
BUFGMUX i_div_clk_gbuf ( end else if (SIM_DEVICE == "ULTRASCALE") begin
.I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
.I1(clk_div_2_s), // 1-bit input: Clock input (S=1) BUFGCE_DIV #(
.BUFGCE_DIVIDE(SEL_0_DIV)
) clk_divide_sel_0 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_sel_0_s));
BUFGCE_DIV #(
.BUFGCE_DIVIDE(SEL_1_DIV)
) clk_divide_sel_1 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_sel_1_s));
end endgenerate
BUFGMUX_CTRL i_div_clk_gbuf (
.I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0)
.I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1)
.S(clk_sel), .S(clk_sel),
.O (clk_out)); .O (clk_out));

2
library/util_clkdiv/util_clkdiv_constr.xdc Normal file
View File

@ -0,0 +1,2 @@
set_clock_groups -group [get_clocks clk_div_sel_0_s] -group [get_clocks clk_div_sel_1_s] -logically_exclusive
set_false_path -to [get_pins i_div_clk_gbuf/S*]

15
library/util_clkdiv/util_clkdiv_ip.tcl
View File

@ -3,10 +3,23 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_clkdiv adi_ip_create util_clkdiv
adi_ip_files util_clkdiv [list \ adi_ip_files util_clkdiv [list \
"util_clkdiv.v" ] "util_clkdiv_constr.xdc" \
"util_clkdiv.v" ]
adi_ip_properties_lite util_clkdiv adi_ip_properties_lite util_clkdiv
adi_ip_constraints util_clkdiv [list \
"util_clkdiv_constr.xdc" ]
set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

28
library/xilinx/axi_adxcvr/axi_adxcvr.v
View File

@ -38,7 +38,19 @@
`timescale 1ns/1ps `timescale 1ns/1ps
module axi_adxcvr ( module axi_adxcvr #(
// parameters
parameter integer ID = 0,
parameter integer NUM_OF_LANES = 8,
parameter integer GTH_OR_GTX_N = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4) (
output [ 7:0] up_cm_sel_0, output [ 7:0] up_cm_sel_0,
output up_cm_enb_0, output up_cm_enb_0,
@ -501,14 +513,6 @@ module axi_adxcvr (
input [ 1:0] m_axi_rresp, input [ 1:0] m_axi_rresp,
output m_axi_rready); output m_axi_rready);
// parameters
parameter integer ID = 0;
parameter integer NUM_OF_LANES = 8;
parameter integer GTH_OR_GTX_N = 0;
parameter integer TX_OR_RX_N = 0;
parameter integer QPLL_ENABLE = 1;
// internal signals // internal signals
wire [ 7:0] up_cm_sel; wire [ 7:0] up_cm_sel;
@ -1788,7 +1792,11 @@ module axi_adxcvr (
axi_adxcvr_up #( axi_adxcvr_up #(
.ID (ID), .ID (ID),
.TX_OR_RX_N (TX_OR_RX_N), .TX_OR_RX_N (TX_OR_RX_N),
.QPLL_ENABLE (QPLL_ENABLE)) .QPLL_ENABLE (QPLL_ENABLE),
.LPM_OR_DFE_N (LPM_OR_DFE_N),
.RATE (RATE),
.SYS_CLK_SEL (SYS_CLK_SEL),
.OUT_CLK_SEL (OUT_CLK_SEL))
i_up ( i_up (
.up_cm_sel (up_cm_sel), .up_cm_sel (up_cm_sel),
.up_cm_enb (up_cm_enb), .up_cm_enb (up_cm_enb),

23
library/xilinx/axi_adxcvr/axi_adxcvr_up.v
View File

@ -37,7 +37,17 @@
`timescale 1ns/100ps `timescale 1ns/100ps
module axi_adxcvr_up ( module axi_adxcvr_up #(
// parameters
parameter integer ID = 0,
parameter integer TX_OR_RX_N = 0,
parameter integer QPLL_ENABLE = 1,
parameter LPM_OR_DFE_N = 1,
parameter [ 2:0] RATE = 3'd0,
parameter [ 1:0] SYS_CLK_SEL = 2'd3,
parameter [ 2:0] OUT_CLK_SEL = 3'd4) (
// common // common
@ -104,9 +114,6 @@ module axi_adxcvr_up (
// parameters // parameters
localparam [31:0] VERSION = 32'h00100161; localparam [31:0] VERSION = 32'h00100161;
parameter integer ID = 0;
parameter integer TX_OR_RX_N = 0;
parameter integer QPLL_ENABLE = 1;
// internal registers // internal registers
@ -221,10 +228,10 @@ module axi_adxcvr_up (
always @(negedge up_rstn or posedge up_clk) begin always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin if (up_rstn == 0) begin
up_lpm_dfe_n <= 'd0; up_lpm_dfe_n <= LPM_OR_DFE_N;
up_rate <= 'd0; up_rate <= RATE;
up_sys_clk_sel <= 'd0; up_sys_clk_sel <= SYS_CLK_SEL;
up_out_clk_sel <= 'd0; up_out_clk_sel <= OUT_CLK_SEL;
end else begin end else begin
if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin
up_lpm_dfe_n <= up_wdata[12]; up_lpm_dfe_n <= up_wdata[12];

151
library/xilinx/common/ad_lvds_in.v
View File

@ -34,68 +34,49 @@
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps `timescale 1ns/100ps
module ad_lvds_in ( module ad_lvds_in #(
// data interface
rx_clk,
rx_data_in_p,
rx_data_in_n,
rx_data_p,
rx_data_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters // parameters
parameter SINGLE_ENDED = 0; parameter SINGLE_ENDED = 0,
parameter DEVICE_TYPE = 0; parameter DEVICE_TYPE = 0,
parameter IODELAY_CTRL = 0; parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group"; parameter IODELAY_GROUP = "dev_if_delay_group") (
localparam VIRTEX7 = 0;
localparam VIRTEX6 = 1;
localparam ULTRASCALE = 2;
// data interface // data interface
input rx_clk; input rx_clk,
input rx_data_in_p; input rx_data_in_p,
input rx_data_in_n; input rx_data_in_n,
output rx_data_p; output rx_data_p,
output rx_data_n; output rx_data_n,
// delay-data interface // delay-data interface
input up_clk; input up_clk,
input up_dld; input up_dld,
input [ 4:0] up_dwdata; input [ 4:0] up_dwdata,
output [ 4:0] up_drdata; output [ 4:0] up_drdata,
// delay-cntrl interface // delay-cntrl interface
input delay_clk; input delay_clk,
input delay_rst; input delay_rst,
output delay_locked; output delay_locked);
// internal parameters
localparam VIRTEX7 = 0;
localparam VIRTEX6 = 1;
localparam ULTRASCALE_PLUS = 2;
localparam ULTRASCALE = 3;
// internal registers // internal registers
reg rx_data_n; reg rx_data_n_d = 'd0;
// internal signals // internal signals
@ -107,21 +88,37 @@ module ad_lvds_in (
// delay controller // delay controller
generate generate
if (IODELAY_CTRL == 1) begin if ((IODELAY_CTRL == 1) && (DEVICE_TYPE == ULTRASCALE_PLUS)) begin
if (DEVICE_TYPE == ULTRASCALE) begin
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl ( IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl (
.RST (delay_rst), .RST (delay_rst),
.REFCLK (delay_clk), .REFCLK (delay_clk),
.RDY (delay_locked)); .RDY (delay_locked));
end else begin end
endgenerate
generate
if ((IODELAY_CTRL == 1) && (DEVICE_TYPE == ULTRASCALE)) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end
endgenerate
generate
if ((IODELAY_CTRL == 1) && ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6))) begin
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl ( IDELAYCTRL i_delay_ctrl (
.RST (delay_rst), .RST (delay_rst),
.REFCLK (delay_clk), .REFCLK (delay_clk),
.RDY (delay_locked)); .RDY (delay_locked));
end end
end else begin endgenerate
generate
if (IODELAY_CTRL == 0) begin
assign delay_locked = 1'b1; assign delay_locked = 1'b1;
end end
endgenerate endgenerate
@ -141,6 +138,8 @@ module ad_lvds_in (
end end
endgenerate endgenerate
// idelay
generate generate
if (DEVICE_TYPE == VIRTEX6) begin if (DEVICE_TYPE == VIRTEX6) begin
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)
@ -204,7 +203,7 @@ module ad_lvds_in (
assign up_drdata = up_drdata_s[8:4]; assign up_drdata = up_drdata_s[8:4];
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE3 #( IDELAYE3 #(
.SIM_DEVICE ("ULTRASCALE_PLUS_ES1"), .SIM_DEVICE ("ULTRASCALE"),
.DELAY_SRC ("IDATAIN"), .DELAY_SRC ("IDATAIN"),
.DELAY_TYPE ("VAR_LOAD"), .DELAY_TYPE ("VAR_LOAD"),
.REFCLK_FREQUENCY (200.0), .REFCLK_FREQUENCY (200.0),
@ -227,6 +226,36 @@ module ad_lvds_in (
end end
endgenerate endgenerate
generate
if (DEVICE_TYPE == ULTRASCALE_PLUS) begin
assign up_drdata = up_drdata_s[8:4];
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE3 #(
.SIM_DEVICE ("ULTRASCALE_PLUS_ES1"),
.DELAY_SRC ("IDATAIN"),
.DELAY_TYPE ("VAR_LOAD"),
.REFCLK_FREQUENCY (200.0),
.DELAY_FORMAT ("COUNT"))
i_rx_data_idelay (
.CASC_RETURN (1'b0),
.CASC_IN (1'b0),
.CASC_OUT (),
.CE (1'b0),
.CLK (up_clk),
.INC (1'b0),
.LOAD (up_dld),
.CNTVALUEIN ({up_dwdata, 4'd0}),
.CNTVALUEOUT (up_drdata_s),
.DATAIN (1'b0),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (1'b0),
.EN_VTC (~up_dld));
end
endgenerate
// iddr
generate generate
if (DEVICE_TYPE == ULTRASCALE) begin if (DEVICE_TYPE == ULTRASCALE) begin
IDDRE1 #( IDDRE1 #(
@ -238,7 +267,25 @@ module ad_lvds_in (
.D (rx_data_idelay_s), .D (rx_data_idelay_s),
.Q1 (rx_data_p), .Q1 (rx_data_p),
.Q2 (rx_data_n_s)); .Q2 (rx_data_n_s));
end else begin end
endgenerate
generate
if (DEVICE_TYPE == ULTRASCALE_PLUS) begin
IDDRE1 #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
i_rx_data_iddr (
.R (1'b0),
.C (rx_clk),
.CB (~rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n_s));
end
endgenerate
generate
if ((DEVICE_TYPE == VIRTEX7) || (DEVICE_TYPE == VIRTEX6)) begin
IDDR #( IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.INIT_Q1 (1'b0), .INIT_Q1 (1'b0),
@ -255,8 +302,10 @@ module ad_lvds_in (
end end
endgenerate endgenerate
assign rx_data_n = rx_data_n_d;
always @(posedge rx_clk) begin always @(posedge rx_clk) begin
rx_data_n <= rx_data_n_s; rx_data_n_d <= rx_data_n_s;
end end
endmodule endmodule

4
projects/common/kcu105/kcu105_system_bd.tcl
View File

@ -95,6 +95,10 @@ set_property -dict [list CONFIG.ETHERNET_BOARD_INTERFACE {sgmii_lvds}] $axi_ethe
set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet set_property -dict [list CONFIG.MDIO_BOARD_INTERFACE {mdio_mdc}] $axi_ethernet
set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet set_property -dict [list CONFIG.DIFFCLK_BOARD_INTERFACE {sgmii_phyclk}] $axi_ethernet
set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet set_property -dict [list CONFIG.PHYRST_BOARD_INTERFACE {phy_reset_out}] $axi_ethernet
set_property -dict [list CONFIG.TXCSUM {Full}] $axi_ethernet
set_property -dict [list CONFIG.RXCSUM {Full}] $axi_ethernet
set_property -dict [list CONFIG.TXMEM {8k}] $axi_ethernet
set_property -dict [list CONFIG.RXMEM {8k}] $axi_ethernet
set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma] set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma]
set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma set_property -dict [list CONFIG.c_include_mm2s_dre {1}] $axi_ethernet_dma

12
projects/daq3/a10gx/system_top.v
View File

@ -209,12 +209,14 @@ module system_top (
// gpio in & out are separate cores // gpio in & out are separate cores
assign sysref = gpio_o[43]; assign gpio_i[63:40] = gpio_o[63:40];
assign adc_pd = gpio_o[42]; assign sysref = gpio_o[40];
assign dac_txen = gpio_o[41]; assign gpio_i[39:39] = trig;
assign gpio_i[38:37] = gpio_o[38:37];
assign adc_pd = gpio_o[38];
assign dac_txen = gpio_o[37];
assign gpio_i[63:38] = gpio_o[63:38];
assign gpio_i[37:37] = trig;
assign gpio_i[36:36] = adc_fdb; assign gpio_i[36:36] = adc_fdb;
assign gpio_i[35:35] = adc_fda; assign gpio_i[35:35] = adc_fda;
assign gpio_i[34:34] = dac_irq; assign gpio_i[34:34] = dac_irq;

12
projects/daq3/kcu105/system_constr.xdc
View File

@ -38,10 +38,10 @@ set_property -dict {PACKAGE_PIN E8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [g
# clocks # clocks
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK] create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK] create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe3_channel/RXOUTCLK]
# gt pin assignments below are for reference only and are ignored by the tool! # gt pin assignments below are for reference only and are ignored by the tool!
@ -67,6 +67,6 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *
set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}] set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}]
set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}] set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]

11
projects/daq3/zc706/system_constr.xdc
View File

@ -52,8 +52,11 @@ set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
# clocks # clocks
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name tx_ref_clk -period 1.60 [get_ports tx_ref_clk_p]
create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p]
create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*]

6
projects/daq3/zc706/system_project.tcl
View File

@ -14,10 +14,8 @@ adi_project_files daq3_zc706 [list \
"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
set_property part "xc7z045ffg900-3" [current_project] set_property part "xc7z045ffg900-3" [get_runs synth_1]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc] set_property part "xc7z045ffg900-3" [get_runs impl_1]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run daq3_zc706 adi_project_run daq3_zc706

6
projects/fmcomms2/ac701/Makefile
View File

@ -20,7 +20,9 @@ M_DEPS += ../../common/ac701/ac701_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -54,7 +56,9 @@ clean:
clean-all:clean clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -68,7 +72,9 @@ fmcomms2_ac701.sdk/system_top.hdf: $(M_DEPS)
lib: lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

217
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -66,88 +66,127 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync] set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
# connections # connections
ad_connect sys_200m_clk axi_ad9361/delay_clk ad_connect sys_200m_clk axi_ad9361/delay_clk
ad_connect axi_ad9361_clk axi_ad9361/l_clk ad_connect axi_ad9361_clk axi_ad9361/l_clk
ad_connect axi_ad9361_clk axi_ad9361/clk ad_connect axi_ad9361_clk axi_ad9361/clk
ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p ad_connect rx_clk_in_p axi_ad9361/rx_clk_in_p
ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n ad_connect rx_clk_in_n axi_ad9361/rx_clk_in_n
ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p ad_connect rx_frame_in_p axi_ad9361/rx_frame_in_p
ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n ad_connect rx_frame_in_n axi_ad9361/rx_frame_in_n
ad_connect rx_data_in_p axi_ad9361/rx_data_in_p ad_connect rx_data_in_p axi_ad9361/rx_data_in_p
ad_connect rx_data_in_n axi_ad9361/rx_data_in_n ad_connect rx_data_in_n axi_ad9361/rx_data_in_n
ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p ad_connect tx_clk_out_p axi_ad9361/tx_clk_out_p
ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n ad_connect tx_clk_out_n axi_ad9361/tx_clk_out_n
ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p ad_connect tx_frame_out_p axi_ad9361/tx_frame_out_p
ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n ad_connect tx_frame_out_n axi_ad9361/tx_frame_out_n
ad_connect tx_data_out_p axi_ad9361/tx_data_out_p ad_connect tx_data_out_p axi_ad9361/tx_data_out_p
ad_connect tx_data_out_n axi_ad9361/tx_data_out_n ad_connect tx_data_out_n axi_ad9361/tx_data_out_n
ad_connect enable axi_ad9361/enable ad_connect enable axi_ad9361/enable
ad_connect txnrx axi_ad9361/txnrx ad_connect txnrx axi_ad9361/txnrx
ad_connect up_enable axi_ad9361/up_enable ad_connect up_enable axi_ad9361/up_enable
ad_connect up_txnrx axi_ad9361/up_txnrx ad_connect up_txnrx axi_ad9361/up_txnrx
ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1
ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2
ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_fifo/din_enable_1 ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2
ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_fifo/din_valid_1 ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3
ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_fifo/din_data_1 ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3
ad_connect axi_ad9361/adc_enable_i1 util_ad9361_adc_fifo/din_enable_2 ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3
ad_connect axi_ad9361/adc_valid_i1 util_ad9361_adc_fifo/din_valid_2 ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0
ad_connect axi_ad9361/adc_data_i1 util_ad9361_adc_fifo/din_data_2 ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0
ad_connect axi_ad9361/adc_enable_q1 util_ad9361_adc_fifo/din_enable_3 ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0
ad_connect axi_ad9361/adc_valid_q1 util_ad9361_adc_fifo/din_valid_3 ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1
ad_connect axi_ad9361/adc_data_q1 util_ad9361_adc_fifo/din_data_3 ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1
ad_connect util_ad9361_adc_fifo/dout_enable_0 util_ad9361_adc_pack/adc_enable_0 ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1
ad_connect util_ad9361_adc_fifo/dout_valid_0 util_ad9361_adc_pack/adc_valid_0 ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2
ad_connect util_ad9361_adc_fifo/dout_data_0 util_ad9361_adc_pack/adc_data_0 ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2
ad_connect util_ad9361_adc_fifo/dout_enable_1 util_ad9361_adc_pack/adc_enable_1 ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2
ad_connect util_ad9361_adc_fifo/dout_valid_1 util_ad9361_adc_pack/adc_valid_1 ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3
ad_connect util_ad9361_adc_fifo/dout_data_1 util_ad9361_adc_pack/adc_data_1 ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3
ad_connect util_ad9361_adc_fifo/dout_enable_2 util_ad9361_adc_pack/adc_enable_2 ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3
ad_connect util_ad9361_adc_fifo/dout_valid_2 util_ad9361_adc_pack/adc_valid_2 ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en
ad_connect util_ad9361_adc_fifo/dout_data_2 util_ad9361_adc_pack/adc_data_2 ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_fifo/dout_enable_3 util_ad9361_adc_pack/adc_enable_3 ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect util_ad9361_adc_fifo/dout_valid_3 util_ad9361_adc_pack/adc_valid_3 ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/dout_data_3 util_ad9361_adc_pack/adc_data_3 ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en ad_connect axi_ad9361_clk clkdiv/clk
ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk ad_connect axi_ad9361/adc_r1_mode concat_logic/In0
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn ad_connect axi_ad9361/dac_r1_mode concat_logic/In1
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync ad_connect concat_logic/dout clkdiv_sel_logic/Op1
ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res
ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out
ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf
ad_connect dac_fifo/din_clk clkdiv/clk_out
ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
ad_connect axi_ad9361_clk dac_fifo/dout_clk
ad_connect dac_fifo/dout_rst axi_ad9361/rst
ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out
ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
ad_connect util_ad9361_dac_upack/dac_data_0 dac_fifo/din_data_0
ad_connect util_ad9361_dac_upack/dac_data_1 dac_fifo/din_data_1
ad_connect util_ad9361_dac_upack/dac_data_2 dac_fifo/din_data_2
ad_connect util_ad9361_dac_upack/dac_data_3 dac_fifo/din_data_3
ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
ad_connect dac_fifo/dout_data_0 axi_ad9361/dac_data_i0
ad_connect dac_fifo/dout_data_1 axi_ad9361/dac_data_q0
ad_connect dac_fifo/dout_data_2 axi_ad9361/dac_data_i1
ad_connect dac_fifo/dout_data_3 axi_ad9361/dac_data_q1
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
ad_connect tdd_sync_t axi_ad9361/tdd_sync_cntr
ad_connect tdd_sync_o util_ad9361_tdd_sync/sync_out
ad_connect tdd_sync_i util_ad9361_tdd_sync/sync_in
# interconnects # interconnects
@ -166,23 +205,3 @@ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9361_adc_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq ad_cpu_interrupt ps-12 mb-13 axi_ad9361_dac_dma/irq
# ila (adc)
set ila_adc [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_adc]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
set_property -dict [list CONFIG.C_NUM_OF_PROBES {5}] $ila_adc
set_property -dict [list CONFIG.C_PROBE0_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE1_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE2_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
set_property -dict [list CONFIG.C_PROBE4_WIDTH {1}] $ila_adc
ad_connect util_ad9361_adc_fifo/dout_data_0 ila_adc/probe0
ad_connect util_ad9361_adc_fifo/dout_data_1 ila_adc/probe1
ad_connect util_ad9361_adc_fifo/dout_data_2 ila_adc/probe2
ad_connect util_ad9361_adc_fifo/dout_data_3 ila_adc/probe3
ad_connect util_ad9361_adc_fifo/dout_valid_0 ila_adc/probe4
ad_connect sys_cpu_clk ila_adc/clk

6
projects/fmcomms2/kc705/Makefile
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@ -20,7 +20,9 @@ M_DEPS += ../../common/kc705/kc705_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -54,7 +56,9 @@ clean:
clean-all:clean clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -68,7 +72,9 @@ fmcomms2_kc705.sdk/system_top.hdf: $(M_DEPS)
lib: lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/fmcomms2/mitx045/Makefile
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@ -24,7 +24,9 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -62,7 +64,9 @@ clean-all:clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -80,7 +84,9 @@ lib:
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_i2s_adi
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/fmcomms2/vc707/Makefile
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@ -19,7 +19,9 @@ M_DEPS += ../../common/vc707/vc707_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -53,7 +55,9 @@ clean:
clean-all:clean clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -67,7 +71,9 @@ fmcomms2_vc707.sdk/system_top.hdf: $(M_DEPS)
lib: lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/fmcomms2/zc702/Makefile
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@ -22,7 +22,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -59,7 +61,9 @@ clean-all:clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -76,7 +80,9 @@ lib:
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/fmcomms2/zc706/Makefile
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@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -58,7 +60,9 @@ clean-all:clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -75,7 +79,9 @@ lib:
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/fmcomms2/zc706pr/Makefile
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@ -43,7 +43,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -80,7 +82,9 @@ clean-all:clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -97,7 +101,9 @@ lib:
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

2
projects/fmcomms2/zc706pr/system_project.tcl
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@ -4,7 +4,7 @@ source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
set mode 0 set mode 1
if {$::argc > 0} { if {$::argc > 0} {
set mode [lindex $argv 0] set mode [lindex $argv 0]
} }

6
projects/fmcomms2/zcu102/Makefile
View File

@ -18,7 +18,9 @@ M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -52,7 +54,9 @@ clean:
clean-all:clean clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -66,7 +70,9 @@ fmcomms2_zcu102.sdk/system_top.hdf: $(M_DEPS)
lib: lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

2
projects/fmcomms2/zcu102/system_bd.tcl
View File

@ -2,5 +2,7 @@
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
source ../common/fmcomms2_bd.tcl source ../common/fmcomms2_bd.tcl
set_property -dict [list CONFIG.SIM_DEVICE {ULTRASCALE}] $clkdiv
set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361] set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361]

6
projects/fmcomms2/zed/Makefile
View File

@ -23,8 +23,10 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr M_DEPS += ../../../library/util_i2c_mixer/util_i2c_mixer.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -62,8 +64,10 @@ clean-all:clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_i2c_mixer clean make -C ../../../library/util_i2c_mixer clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -81,8 +85,10 @@ lib:
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_i2s_adi
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_i2c_mixer make -C ../../../library/util_i2c_mixer
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

3
projects/fmcomms5/Makefile
View File

@ -9,16 +9,19 @@
all: all:
-make -C zc702 all -make -C zc702 all
-make -C zc706 all -make -C zc706 all
-make -C zcu102 all
clean: clean:
make -C zc702 clean make -C zc702 clean
make -C zc706 clean make -C zc706 clean
make -C zcu102 clean
clean-all: clean-all:
make -C zc702 clean-all make -C zc702 clean-all
make -C zc706 clean-all make -C zc706 clean-all
make -C zcu102 clean-all
#################################################################################### ####################################################################################
#################################################################################### ####################################################################################

257
projects/fmcomms5/common/fmcomms5_bd.tcl
View File

@ -99,60 +99,89 @@ set_property -dict [list CONFIG.DIN_DATA_WIDTH {16} ] $adc_wfifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16} ] $adc_wfifo set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16} ] $adc_wfifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $adc_wfifo set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $adc_wfifo
set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $dac_fifo
set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
set_property -dict [list CONFIG.C_SIZE {4}] $clkdiv_sel_logic
set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
set_property -dict [list CONFIG.NUM_PORTS {4}] $concat_logic
# connections (ad9361) # connections (ad9361)
ad_connect sys_200m_clk axi_ad9361_0/delay_clk ad_connect sys_200m_clk axi_ad9361_0/delay_clk
ad_connect sys_200m_clk axi_ad9361_1/delay_clk ad_connect sys_200m_clk axi_ad9361_1/delay_clk
ad_connect axi_ad9361_0_clk axi_ad9361_0/l_clk ad_connect axi_ad9361_0_clk axi_ad9361_0/l_clk
ad_connect axi_ad9361_1_clk axi_ad9361_1/l_clk ad_connect axi_ad9361_1_clk axi_ad9361_1/l_clk
ad_connect axi_ad9361_0_clk axi_ad9361_0/clk ad_connect axi_ad9361_0_clk axi_ad9361_0/clk
ad_connect axi_ad9361_0_clk axi_ad9361_1/clk ad_connect axi_ad9361_0_clk axi_ad9361_1/clk
ad_connect axi_ad9361_0/rst adc_wfifo/din_rst ad_connect axi_ad9361_0_clk adc_wfifo/din_clk
ad_connect axi_ad9361_0_clk adc_wfifo/din_clk ad_connect axi_ad9361_0_clk clkdiv/clk
ad_connect sys_cpu_clk adc_wfifo/dout_clk ad_connect axi_ad9361_0_clk dac_fifo/dout_clk
ad_connect sys_cpu_resetn adc_wfifo/dout_rstn ad_connect axi_ad9361_0/rst adc_wfifo/din_rst
ad_connect sys_cpu_clk util_cpack_adc/adc_clk ad_connect axi_ad9361_0/rst dac_fifo/dout_rst
ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
ad_connect axi_ad9361_0_clk util_upack_dac/dac_clk ad_connect clkdiv/clk_out adc_wfifo/dout_clk
ad_connect axi_ad9361_0_clk axi_ad9361_dac_dma/fifo_rd_clk ad_connect clkdiv/clk_out util_cpack_adc/adc_clk
ad_connect sys_cpu_resetn sys_100m_resetn ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn ad_connect clkdiv/clk_out dac_fifo/din_clk
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn ad_connect clkdiv/clk_out clkdiv_reset/slowest_sync_clk
ad_connect sys_cpu_reset util_cpack_adc/adc_rst ad_connect clkdiv/clk_out util_upack_dac/dac_clk
ad_connect sys_cpu_resetn sys_100m_resetn
ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect clkdiv_reset/peripheral_reset util_cpack_adc/adc_rst
ad_connect clkdiv_reset/peripheral_aresetn dac_fifo/din_rstn
ad_connect clkdiv_reset/peripheral_aresetn adc_wfifo/dout_rstn
ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_out
ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in ad_connect axi_ad9361_0_dac_sync axi_ad9361_0/dac_sync_in
ad_connect axi_ad9361_0_dac_sync axi_ad9361_1/dac_sync_in ad_connect axi_ad9361_0_dac_sync axi_ad9361_1/dac_sync_in
ad_connect rx_clk_in_0_p axi_ad9361_0/rx_clk_in_p ad_connect rx_clk_in_0_p axi_ad9361_0/rx_clk_in_p
ad_connect rx_clk_in_0_n axi_ad9361_0/rx_clk_in_n ad_connect rx_clk_in_0_n axi_ad9361_0/rx_clk_in_n
ad_connect rx_frame_in_0_p axi_ad9361_0/rx_frame_in_p ad_connect rx_frame_in_0_p axi_ad9361_0/rx_frame_in_p
ad_connect rx_frame_in_0_n axi_ad9361_0/rx_frame_in_n ad_connect rx_frame_in_0_n axi_ad9361_0/rx_frame_in_n
ad_connect rx_data_in_0_p axi_ad9361_0/rx_data_in_p ad_connect rx_data_in_0_p axi_ad9361_0/rx_data_in_p
ad_connect rx_data_in_0_n axi_ad9361_0/rx_data_in_n ad_connect rx_data_in_0_n axi_ad9361_0/rx_data_in_n
ad_connect tx_clk_out_0_p axi_ad9361_0/tx_clk_out_p ad_connect tx_clk_out_0_p axi_ad9361_0/tx_clk_out_p
ad_connect tx_clk_out_0_n axi_ad9361_0/tx_clk_out_n ad_connect tx_clk_out_0_n axi_ad9361_0/tx_clk_out_n
ad_connect tx_frame_out_0_p axi_ad9361_0/tx_frame_out_p ad_connect tx_frame_out_0_p axi_ad9361_0/tx_frame_out_p
ad_connect tx_frame_out_0_n axi_ad9361_0/tx_frame_out_n ad_connect tx_frame_out_0_n axi_ad9361_0/tx_frame_out_n
ad_connect tx_data_out_0_p axi_ad9361_0/tx_data_out_p ad_connect tx_data_out_0_p axi_ad9361_0/tx_data_out_p
ad_connect tx_data_out_0_n axi_ad9361_0/tx_data_out_n ad_connect tx_data_out_0_n axi_ad9361_0/tx_data_out_n
ad_connect rx_clk_in_1_p axi_ad9361_1/rx_clk_in_p ad_connect rx_clk_in_1_p axi_ad9361_1/rx_clk_in_p
ad_connect rx_clk_in_1_n axi_ad9361_1/rx_clk_in_n ad_connect rx_clk_in_1_n axi_ad9361_1/rx_clk_in_n
ad_connect rx_frame_in_1_p axi_ad9361_1/rx_frame_in_p ad_connect rx_frame_in_1_p axi_ad9361_1/rx_frame_in_p
ad_connect rx_frame_in_1_n axi_ad9361_1/rx_frame_in_n ad_connect rx_frame_in_1_n axi_ad9361_1/rx_frame_in_n
ad_connect rx_data_in_1_p axi_ad9361_1/rx_data_in_p ad_connect rx_data_in_1_p axi_ad9361_1/rx_data_in_p
ad_connect rx_data_in_1_n axi_ad9361_1/rx_data_in_n ad_connect rx_data_in_1_n axi_ad9361_1/rx_data_in_n
ad_connect tx_clk_out_1_p axi_ad9361_1/tx_clk_out_p ad_connect tx_clk_out_1_p axi_ad9361_1/tx_clk_out_p
ad_connect tx_clk_out_1_n axi_ad9361_1/tx_clk_out_n ad_connect tx_clk_out_1_n axi_ad9361_1/tx_clk_out_n
ad_connect tx_frame_out_1_p axi_ad9361_1/tx_frame_out_p ad_connect tx_frame_out_1_p axi_ad9361_1/tx_frame_out_p
ad_connect tx_frame_out_1_n axi_ad9361_1/tx_frame_out_n ad_connect tx_frame_out_1_n axi_ad9361_1/tx_frame_out_n
ad_connect tx_data_out_1_p axi_ad9361_1/tx_data_out_p ad_connect tx_data_out_1_p axi_ad9361_1/tx_data_out_p
ad_connect tx_data_out_1_n axi_ad9361_1/tx_data_out_n ad_connect tx_data_out_1_n axi_ad9361_1/tx_data_out_n
ad_connect concat_logic/In0 axi_ad9361_0/adc_r1_mode
ad_connect concat_logic/In1 axi_ad9361_0/dac_r1_mode
ad_connect concat_logic/In2 axi_ad9361_1/adc_r1_mode
ad_connect concat_logic/In3 axi_ad9361_1/dac_r1_mode
ad_connect concat_logic/dout clkdiv_sel_logic/Op1
ad_connect clkdiv_sel_logic/Res clkdiv/clk_sel
ad_connect adc_wfifo/dout_ovf axi_ad9361_0/adc_dovf
ad_connect axi_ad9361_0/adc_enable_i0 adc_wfifo/din_enable_0 ad_connect axi_ad9361_0/adc_enable_i0 adc_wfifo/din_enable_0
ad_connect axi_ad9361_0/adc_valid_i0 adc_wfifo/din_valid_0 ad_connect axi_ad9361_0/adc_valid_i0 adc_wfifo/din_valid_0
ad_connect axi_ad9361_0/adc_data_i0 adc_wfifo/din_data_0 ad_connect axi_ad9361_0/adc_data_i0 adc_wfifo/din_data_0
ad_connect axi_ad9361_0/adc_enable_q0 adc_wfifo/din_enable_1 ad_connect axi_ad9361_0/adc_enable_q0 adc_wfifo/din_enable_1
@ -175,64 +204,92 @@ ad_connect axi_ad9361_1/adc_valid_i1 adc_wfifo/din_valid_6
ad_connect axi_ad9361_1/adc_data_i1 adc_wfifo/din_data_6 ad_connect axi_ad9361_1/adc_data_i1 adc_wfifo/din_data_6
ad_connect axi_ad9361_1/adc_enable_q1 adc_wfifo/din_enable_7 ad_connect axi_ad9361_1/adc_enable_q1 adc_wfifo/din_enable_7
ad_connect axi_ad9361_1/adc_valid_q1 adc_wfifo/din_valid_7 ad_connect axi_ad9361_1/adc_valid_q1 adc_wfifo/din_valid_7
ad_connect axi_ad9361_1/adc_data_q1 adc_wfifo/din_data_7 ad_connect axi_ad9361_1/adc_data_q1 adc_wfifo/din_data_7
ad_connect util_cpack_adc/adc_enable_0 adc_wfifo/dout_enable_0 ad_connect util_cpack_adc/adc_enable_0 adc_wfifo/dout_enable_0
ad_connect util_cpack_adc/adc_valid_0 adc_wfifo/dout_valid_0 ad_connect util_cpack_adc/adc_valid_0 adc_wfifo/dout_valid_0
ad_connect util_cpack_adc/adc_data_0 adc_wfifo/dout_data_0 ad_connect util_cpack_adc/adc_data_0 adc_wfifo/dout_data_0
ad_connect util_cpack_adc/adc_enable_1 adc_wfifo/dout_enable_1 ad_connect util_cpack_adc/adc_enable_1 adc_wfifo/dout_enable_1
ad_connect util_cpack_adc/adc_valid_1 adc_wfifo/dout_valid_1 ad_connect util_cpack_adc/adc_valid_1 adc_wfifo/dout_valid_1
ad_connect util_cpack_adc/adc_data_1 adc_wfifo/dout_data_1 ad_connect util_cpack_adc/adc_data_1 adc_wfifo/dout_data_1
ad_connect util_cpack_adc/adc_enable_2 adc_wfifo/dout_enable_2 ad_connect util_cpack_adc/adc_enable_2 adc_wfifo/dout_enable_2
ad_connect util_cpack_adc/adc_valid_2 adc_wfifo/dout_valid_2 ad_connect util_cpack_adc/adc_valid_2 adc_wfifo/dout_valid_2
ad_connect util_cpack_adc/adc_data_2 adc_wfifo/dout_data_2 ad_connect util_cpack_adc/adc_data_2 adc_wfifo/dout_data_2
ad_connect util_cpack_adc/adc_enable_3 adc_wfifo/dout_enable_3 ad_connect util_cpack_adc/adc_enable_3 adc_wfifo/dout_enable_3
ad_connect util_cpack_adc/adc_valid_3 adc_wfifo/dout_valid_3 ad_connect util_cpack_adc/adc_valid_3 adc_wfifo/dout_valid_3
ad_connect util_cpack_adc/adc_data_3 adc_wfifo/dout_data_3 ad_connect util_cpack_adc/adc_data_3 adc_wfifo/dout_data_3
ad_connect util_cpack_adc/adc_enable_4 adc_wfifo/dout_enable_4 ad_connect util_cpack_adc/adc_enable_4 adc_wfifo/dout_enable_4
ad_connect util_cpack_adc/adc_valid_4 adc_wfifo/dout_valid_4 ad_connect util_cpack_adc/adc_valid_4 adc_wfifo/dout_valid_4
ad_connect util_cpack_adc/adc_data_4 adc_wfifo/dout_data_4 ad_connect util_cpack_adc/adc_data_4 adc_wfifo/dout_data_4
ad_connect util_cpack_adc/adc_enable_5 adc_wfifo/dout_enable_5 ad_connect util_cpack_adc/adc_enable_5 adc_wfifo/dout_enable_5
ad_connect util_cpack_adc/adc_valid_5 adc_wfifo/dout_valid_5 ad_connect util_cpack_adc/adc_valid_5 adc_wfifo/dout_valid_5
ad_connect util_cpack_adc/adc_data_5 adc_wfifo/dout_data_5 ad_connect util_cpack_adc/adc_data_5 adc_wfifo/dout_data_5
ad_connect util_cpack_adc/adc_enable_6 adc_wfifo/dout_enable_6 ad_connect util_cpack_adc/adc_enable_6 adc_wfifo/dout_enable_6
ad_connect util_cpack_adc/adc_valid_6 adc_wfifo/dout_valid_6 ad_connect util_cpack_adc/adc_valid_6 adc_wfifo/dout_valid_6
ad_connect util_cpack_adc/adc_data_6 adc_wfifo/dout_data_6 ad_connect util_cpack_adc/adc_data_6 adc_wfifo/dout_data_6
ad_connect util_cpack_adc/adc_enable_7 adc_wfifo/dout_enable_7 ad_connect util_cpack_adc/adc_enable_7 adc_wfifo/dout_enable_7
ad_connect util_cpack_adc/adc_valid_7 adc_wfifo/dout_valid_7 ad_connect util_cpack_adc/adc_valid_7 adc_wfifo/dout_valid_7
ad_connect util_cpack_adc/adc_data_7 adc_wfifo/dout_data_7 ad_connect util_cpack_adc/adc_data_7 adc_wfifo/dout_data_7
ad_connect util_cpack_adc/adc_valid axi_ad9361_adc_dma/fifo_wr_en ad_connect util_cpack_adc/adc_valid axi_ad9361_adc_dma/fifo_wr_en
ad_connect util_cpack_adc/adc_sync axi_ad9361_adc_dma/fifo_wr_sync ad_connect util_cpack_adc/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_cpack_adc/adc_data axi_ad9361_adc_dma/fifo_wr_din ad_connect util_cpack_adc/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_0/dac_enable_i0 util_upack_dac/dac_enable_0
ad_connect axi_ad9361_0/dac_valid_i0 util_upack_dac/dac_valid_0 ad_connect dac_fifo/din_enable_0 util_upack_dac/dac_enable_0
ad_connect axi_ad9361_0/dac_data_i0 util_upack_dac/dac_data_0 ad_connect dac_fifo/din_valid_0 util_upack_dac/dac_valid_0
ad_connect axi_ad9361_0/dac_enable_q0 util_upack_dac/dac_enable_1 ad_connect dac_fifo/din_data_0 util_upack_dac/dac_data_0
ad_connect axi_ad9361_0/dac_valid_q0 util_upack_dac/dac_valid_1 ad_connect dac_fifo/din_enable_1 util_upack_dac/dac_enable_1
ad_connect axi_ad9361_0/dac_data_q0 util_upack_dac/dac_data_1 ad_connect dac_fifo/din_valid_1 util_upack_dac/dac_valid_1
ad_connect axi_ad9361_0/dac_enable_i1 util_upack_dac/dac_enable_2 ad_connect dac_fifo/din_data_1 util_upack_dac/dac_data_1
ad_connect axi_ad9361_0/dac_valid_i1 util_upack_dac/dac_valid_2 ad_connect dac_fifo/din_enable_2 util_upack_dac/dac_enable_2
ad_connect axi_ad9361_0/dac_data_i1 util_upack_dac/dac_data_2 ad_connect dac_fifo/din_valid_2 util_upack_dac/dac_valid_2
ad_connect axi_ad9361_0/dac_enable_q1 util_upack_dac/dac_enable_3 ad_connect dac_fifo/din_data_2 util_upack_dac/dac_data_2
ad_connect axi_ad9361_0/dac_valid_q1 util_upack_dac/dac_valid_3 ad_connect dac_fifo/din_enable_3 util_upack_dac/dac_enable_3
ad_connect axi_ad9361_0/dac_data_q1 util_upack_dac/dac_data_3 ad_connect dac_fifo/din_valid_3 util_upack_dac/dac_valid_3
ad_connect axi_ad9361_1/dac_enable_i0 util_upack_dac/dac_enable_4 ad_connect dac_fifo/din_data_3 util_upack_dac/dac_data_3
ad_connect axi_ad9361_1/dac_valid_i0 util_upack_dac/dac_valid_4 ad_connect dac_fifo/din_enable_4 util_upack_dac/dac_enable_4
ad_connect axi_ad9361_1/dac_data_i0 util_upack_dac/dac_data_4 ad_connect dac_fifo/din_valid_4 util_upack_dac/dac_valid_4
ad_connect axi_ad9361_1/dac_enable_q0 util_upack_dac/dac_enable_5 ad_connect dac_fifo/din_data_4 util_upack_dac/dac_data_4
ad_connect axi_ad9361_1/dac_valid_q0 util_upack_dac/dac_valid_5 ad_connect dac_fifo/din_enable_5 util_upack_dac/dac_enable_5
ad_connect axi_ad9361_1/dac_data_q0 util_upack_dac/dac_data_5 ad_connect dac_fifo/din_valid_5 util_upack_dac/dac_valid_5
ad_connect axi_ad9361_1/dac_enable_i1 util_upack_dac/dac_enable_6 ad_connect dac_fifo/din_data_5 util_upack_dac/dac_data_5
ad_connect axi_ad9361_1/dac_valid_i1 util_upack_dac/dac_valid_6 ad_connect dac_fifo/din_enable_6 util_upack_dac/dac_enable_6
ad_connect axi_ad9361_1/dac_data_i1 util_upack_dac/dac_data_6 ad_connect dac_fifo/din_valid_6 util_upack_dac/dac_valid_6
ad_connect axi_ad9361_1/dac_enable_q1 util_upack_dac/dac_enable_7 ad_connect dac_fifo/din_data_6 util_upack_dac/dac_data_6
ad_connect axi_ad9361_1/dac_valid_q1 util_upack_dac/dac_valid_7 ad_connect dac_fifo/din_enable_7 util_upack_dac/dac_enable_7
ad_connect axi_ad9361_1/dac_data_q1 util_upack_dac/dac_data_7 ad_connect dac_fifo/din_valid_7 util_upack_dac/dac_valid_7
ad_connect util_upack_dac/dac_valid axi_ad9361_dac_dma/fifo_rd_en ad_connect dac_fifo/din_data_7 util_upack_dac/dac_data_7
ad_connect util_upack_dac/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_0/adc_dovf axi_ad9361_adc_dma/fifo_wr_overflow ad_connect util_upack_dac/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect axi_ad9361_0/dac_dunf axi_ad9361_dac_dma/fifo_rd_underflow ad_connect util_upack_dac/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_0/dac_enable_i0 dac_fifo/dout_enable_0
ad_connect axi_ad9361_0/dac_valid_i0 dac_fifo/dout_valid_0
ad_connect axi_ad9361_0/dac_data_i0 dac_fifo/dout_data_0
ad_connect axi_ad9361_0/dac_enable_q0 dac_fifo/dout_enable_1
ad_connect axi_ad9361_0/dac_valid_q0 dac_fifo/dout_valid_1
ad_connect axi_ad9361_0/dac_data_q0 dac_fifo/dout_data_1
ad_connect axi_ad9361_0/dac_enable_i1 dac_fifo/dout_enable_2
ad_connect axi_ad9361_0/dac_valid_i1 dac_fifo/dout_valid_2
ad_connect axi_ad9361_0/dac_data_i1 dac_fifo/dout_data_2
ad_connect axi_ad9361_0/dac_enable_q1 dac_fifo/dout_enable_3
ad_connect axi_ad9361_0/dac_valid_q1 dac_fifo/dout_valid_3
ad_connect axi_ad9361_0/dac_data_q1 dac_fifo/dout_data_3
ad_connect axi_ad9361_1/dac_enable_i0 dac_fifo/dout_enable_4
ad_connect axi_ad9361_1/dac_valid_i0 dac_fifo/dout_valid_4
ad_connect axi_ad9361_1/dac_data_i0 dac_fifo/dout_data_4
ad_connect axi_ad9361_1/dac_enable_q0 dac_fifo/dout_enable_5
ad_connect axi_ad9361_1/dac_valid_q0 dac_fifo/dout_valid_5
ad_connect axi_ad9361_1/dac_data_q0 dac_fifo/dout_data_5
ad_connect axi_ad9361_1/dac_enable_i1 dac_fifo/dout_enable_6
ad_connect axi_ad9361_1/dac_valid_i1 dac_fifo/dout_valid_6
ad_connect axi_ad9361_1/dac_data_i1 dac_fifo/dout_data_6
ad_connect axi_ad9361_1/dac_enable_q1 dac_fifo/dout_enable_7
ad_connect axi_ad9361_1/dac_valid_q1 dac_fifo/dout_valid_7
ad_connect axi_ad9361_1/dac_data_q1 dac_fifo/dout_data_7
ad_connect axi_ad9361_0/dac_dunf dac_fifo/dout_unf
ad_connect axi_ad9361_1/dac_dunf dac_fifo/dout_unf
ad_connect axi_ad9361_0/up_enable up_enable_0 ad_connect axi_ad9361_0/up_enable up_enable_0
ad_connect axi_ad9361_0/up_txnrx up_txnrx_0 ad_connect axi_ad9361_0/up_txnrx up_txnrx_0

6
projects/fmcomms5/zc702/Makefile
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@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -57,7 +59,9 @@ clean-all:clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -73,7 +77,9 @@ lib:
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/fmcomms5/zc706/Makefile
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@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -57,7 +59,9 @@ clean-all:clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -73,7 +77,9 @@ lib:
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

78
projects/fmcomms5/zcu102/Makefile Normal file
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@ -0,0 +1,78 @@
####################################################################################
####################################################################################
## Copyright 2011(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
####################################################################################
M_DEPS += system_top.v
M_DEPS += system_project.tcl
M_DEPS += system_constr.xdc
M_DEPS += system_bd.tcl
M_DEPS += ../common/fmcomms5_bd.tcl
M_DEPS += ../../scripts/adi_project.tcl
M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
M_VIVADO := vivado -mode batch -source
M_FLIST := *.cache
M_FLIST += *.data
M_FLIST += *.xpr
M_FLIST += *.log
M_FLIST += *.jou
M_FLIST += xgui
M_FLIST += *.runs
M_FLIST += *.srcs
M_FLIST += *.sdk
M_FLIST += *.hw
M_FLIST += *.sim
M_FLIST += .Xil
M_FLIST += *.ip_user_files
.PHONY: all lib clean clean-all
all: lib fmcomms5_zcu102.sdk/system_top.hdf
clean:
rm -rf $(M_FLIST)
clean-all:clean
make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean
fmcomms5_zcu102.sdk/system_top.hdf: $(M_DEPS)
-rm -rf $(M_FLIST)
$(M_VIVADO) system_project.tcl >> fmcomms5_zcu102_vivado.log 2>&1
lib:
make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_upack
make -C ../../../library/util_wfifo
####################################################################################
####################################################################################

12
projects/fmcomms5/zcu102/system_bd.tcl Normal file
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@ -0,0 +1,12 @@
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
set_property -dict [list CONFIG.PSU__FPGA_PL2_ENABLE {1}] $sys_ps8
set_property -dict [list CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {200}] $sys_ps8
ad_connect sys_dma_clk sys_ps8/pl_clk2
source ../common/fmcomms5_bd.tcl
set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_0]
set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_1]
set_property -dict [list CONFIG.SIM_DEVICE {ULTRASCALE}] $clkdiv

135
projects/fmcomms5/zcu102/system_constr.xdc Normal file
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@ -0,0 +1,135 @@
# constraints
# ad9361 master
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## D20 FMC_HPC0_LA17_CC_P
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## D21 FMC_HPC0_LA17_CC_N
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_0_p] ; ## G06 FMC_HPC0_LA00_CC_P
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_0_n] ; ## G07 FMC_HPC0_LA00_CC_N
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_0_p] ; ## D08 FMC_HPC0_LA01_CC_P
set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_0_n] ; ## D09 FMC_HPC0_LA01_CC_N
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[0]] ; ## H07 FMC_HPC0_LA02_P
set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[0]] ; ## H08 FMC_HPC0_LA02_N
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[1]] ; ## G09 FMC_HPC0_LA03_P
set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[1]] ; ## G10 FMC_HPC0_LA03_N
set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[2]] ; ## H10 FMC_HPC0_LA04_P
set_property -dict {PACKAGE_PIN AA1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[2]] ; ## H11 FMC_HPC0_LA04_N
set_property -dict {PACKAGE_PIN AB3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[3]] ; ## D11 FMC_HPC0_LA05_P
set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[3]] ; ## D12 FMC_HPC0_LA05_N
set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[4]] ; ## C10 FMC_HPC0_LA06_P
set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[4]] ; ## C11 FMC_HPC0_LA06_N
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_p[5]] ; ## H13 FMC_HPC0_LA07_P
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_0_n[5]] ; ## H14 FMC_HPC0_LA07_N
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports tx_clk_out_0_p] ; ## G12 FMC_HPC0_LA08_P
set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVDS} [get_ports tx_clk_out_0_n] ; ## G13 FMC_HPC0_LA08_N
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVDS} [get_ports tx_frame_out_0_p] ; ## D14 FMC_HPC0_LA09_P
set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVDS} [get_ports tx_frame_out_0_n] ; ## D15 FMC_HPC0_LA09_N
set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[0]] ; ## C14 FMC_HPC0_LA10_P
set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[0]] ; ## C15 FMC_HPC0_LA10_N
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[1]] ; ## H16 FMC_HPC0_LA11_P
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[1]] ; ## H17 FMC_HPC0_LA11_N
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[2]] ; ## G15 FMC_HPC0_LA12_P
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[2]] ; ## G16 FMC_HPC0_LA12_N
set_property -dict {PACKAGE_PIN AB8 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[3]] ; ## D17 FMC_HPC0_LA13_P
set_property -dict {PACKAGE_PIN AC8 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[3]] ; ## D18 FMC_HPC0_LA13_N
set_property -dict {PACKAGE_PIN AC7 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[4]] ; ## C18 FMC_HPC0_LA14_P
set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[4]] ; ## C19 FMC_HPC0_LA14_N
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVDS} [get_ports tx_data_out_0_p[5]] ; ## H19 FMC_HPC0_LA15_P
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVDS} [get_ports tx_data_out_0_n[5]] ; ## H20 FMC_HPC0_LA15_N
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[0]] ; ## H22 FMC_HPC0_LA19_P
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[1]] ; ## H23 FMC_HPC0_LA19_N
set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[2]] ; ## G21 FMC_HPC0_LA20_P
set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[3]] ; ## G22 FMC_HPC0_LA20_N
set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[4]] ; ## H25 FMC_HPC0_LA21_P
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[5]] ; ## H26 FMC_HPC0_LA21_N
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[6]] ; ## G24 FMC_HPC0_LA22_P
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18} [get_ports gpio_status_0[7]] ; ## G25 FMC_HPC0_LA22_N
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[0]] ; ## D23 FMC_HPC0_LA23_P
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[1]] ; ## D24 FMC_HPC0_LA23_N
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[2]] ; ## H28 FMC_HPC0_LA24_P
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_0[3]] ; ## H29 FMC_HPC0_LA24_N
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc_0] ; ## G27 FMC_HPC0_LA25_P
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports mcs_sync] ; ## C22 FMC_HPC0_LA18_CC_P
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports gpio_resetb_0] ; ## C23 FMC_HPC0_LA18_CC_N
set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18} [get_ports enable_0] ; ## G18 FMC_HPC0_LA16_P
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports txnrx_0] ; ## G19 FMC_HPC0_LA16_N
set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_1_0] ; ## C26 FMC_HPC0_LA27_P
set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_2_0] ; ## C27 FMC_HPC0_LA27_N
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_1_0] ; ## D26 FMC_HPC0_LA26_P
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_2_0] ; ## D27 FMC_HPC0_LA26_N
set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS18} [get_ports gpio_ad5355_rfen] ; ## H31 FMC_HPC0_LA28_P
set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports gpio_ad5355_lock] ; ## H37 FMC_HPC0_LA32_P
# spi
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad9361_0] ; ## G30 FMC_HPC0_LA29_P
set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad9361_1] ; ## G31 FMC_HPC0_LA29_N
set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_ad5355] ; ## H34 FMC_HPC0_LA30_P
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports spi_clk] ; ## H35 FMC_HPC0_LA30_N
set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## G33 FMC_HPC0_LA31_P
set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## G34 FMC_HPC0_LA31_N
# ad9361 slave
set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_1_p] ; ## G06 FMC_HPC1_LA00_CC_P
set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_clk_in_1_n] ; ## G07 FMC_HPC1_LA00_CC_N
set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_1_p] ; ## D08 FMC_HPC1_LA01_CC_P
set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_frame_in_1_n] ; ## D09 FMC_HPC1_LA01_CC_N
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[0]] ; ## H07 FMC_HPC1_LA02_P
set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[0]] ; ## H08 FMC_HPC1_LA02_N
set_property -dict {PACKAGE_PIN AH1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[1]] ; ## G09 FMC_HPC1_LA03_P
set_property -dict {PACKAGE_PIN AJ1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[1]] ; ## G10 FMC_HPC1_LA03_N
set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[2]] ; ## H10 FMC_HPC1_LA04_P
set_property -dict {PACKAGE_PIN AF1 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[2]] ; ## H11 FMC_HPC1_LA04_N
set_property -dict {PACKAGE_PIN AG3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[3]] ; ## D11 FMC_HPC1_LA05_P
set_property -dict {PACKAGE_PIN AH3 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[3]] ; ## D12 FMC_HPC1_LA05_N
set_property -dict {PACKAGE_PIN AH2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[4]] ; ## C10 FMC_HPC1_LA06_P
set_property -dict {PACKAGE_PIN AJ2 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[4]] ; ## C11 FMC_HPC1_LA06_N
set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_p[5]] ; ## H13 FMC_HPC1_LA07_P
set_property -dict {PACKAGE_PIN AE4 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports rx_data_in_1_n[5]] ; ## H14 FMC_HPC1_LA07_N
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVDS} [get_ports tx_clk_out_1_p] ; ## G12 FMC_HPC1_LA08_P
set_property -dict {PACKAGE_PIN AF3 IOSTANDARD LVDS} [get_ports tx_clk_out_1_n] ; ## G13 FMC_HPC1_LA08_N
set_property -dict {PACKAGE_PIN AJ6 IOSTANDARD LVDS} [get_ports tx_frame_out_1_p] ; ## D14 FMC_HPC1_LA09_P
set_property -dict {PACKAGE_PIN AJ5 IOSTANDARD LVDS} [get_ports tx_frame_out_1_n] ; ## D15 FMC_HPC1_LA09_N
set_property -dict {PACKAGE_PIN AH4 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[0]] ; ## C14 FMC_HPC1_LA10_P
set_property -dict {PACKAGE_PIN AJ4 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[0]] ; ## C15 FMC_HPC1_LA10_N
set_property -dict {PACKAGE_PIN AE8 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[1]] ; ## H16 FMC_HPC1_LA11_P
set_property -dict {PACKAGE_PIN AF8 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[1]] ; ## H17 FMC_HPC1_LA11_N
set_property -dict {PACKAGE_PIN AD7 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[2]] ; ## G15 FMC_HPC1_LA12_P
set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[2]] ; ## G16 FMC_HPC1_LA12_N
set_property -dict {PACKAGE_PIN AG8 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[3]] ; ## D17 FMC_HPC1_LA13_P
set_property -dict {PACKAGE_PIN AH8 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[3]] ; ## D18 FMC_HPC1_LA13_N
set_property -dict {PACKAGE_PIN AH7 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[4]] ; ## C18 FMC_HPC1_LA14_P
set_property -dict {PACKAGE_PIN AH6 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[4]] ; ## C19 FMC_HPC1_LA14_N
set_property -dict {PACKAGE_PIN AD10 IOSTANDARD LVDS} [get_ports tx_data_out_1_p[5]] ; ## H19 FMC_HPC1_LA15_P
set_property -dict {PACKAGE_PIN AE9 IOSTANDARD LVDS} [get_ports tx_data_out_1_n[5]] ; ## H20 FMC_HPC1_LA15_N
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[0]] ; ## H22 FMC_HPC1_LA19_P
set_property -dict {PACKAGE_PIN AA10 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[1]] ; ## H23 FMC_HPC1_LA19_N
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[2]] ; ## G21 FMC_HPC1_LA20_P
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[3]] ; ## G22 FMC_HPC1_LA20_N
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[4]] ; ## H25 FMC_HPC1_LA21_P
set_property -dict {PACKAGE_PIN AC11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[5]] ; ## H26 FMC_HPC1_LA21_N
set_property -dict {PACKAGE_PIN AF11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[6]] ; ## G24 FMC_HPC1_LA22_P
set_property -dict {PACKAGE_PIN AG11 IOSTANDARD LVCMOS18} [get_ports gpio_status_1[7]] ; ## G25 FMC_HPC1_LA22_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[0]] ; ## D23 FMC_HPC1_LA23_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[1]] ; ## D24 FMC_HPC1_LA23_N
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[2]] ; ## H28 FMC_HPC1_LA24_P
set_property -dict {PACKAGE_PIN AH11 IOSTANDARD LVCMOS18} [get_ports gpio_ctl_1[3]] ; ## H29 FMC_HPC1_LA24_N
set_property -dict {PACKAGE_PIN AE10 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc_1] ; ## G27 FMC_HPC1_LA25_P
set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports gpio_resetb_1] ; ## G30 FMC_HPC1_LA29_P
set_property -dict {PACKAGE_PIN AG10 IOSTANDARD LVCMOS18} [get_ports enable_1] ; ## G18 FMC_HPC1_LA16_P
set_property -dict {PACKAGE_PIN AG9 IOSTANDARD LVCMOS18} [get_ports txnrx_1] ; ## G19 FMC_HPC1_LA16_N
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_3_1] ; ## C26 FMC_HPC1_LA27_P
set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS18} [get_ports gpio_debug_4_1] ; ## C27 FMC_HPC1_LA27_N
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_3_1] ; ## D26 FMC_HPC1_LA26_P
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports gpio_calsw_4_1] ; ## D27 FMC_HPC1_LA26_N
# clocks
create_clock -name rx_0_clk -period 4.00 [get_ports rx_clk_in_0_p]
create_clock -name rx_1_clk -period 4.00 [get_ports rx_clk_in_1_p]
create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361_0/clk]

17
projects/fmcomms5/zcu102/system_project.tcl Normal file
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@ -0,0 +1,17 @@
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcomms5_zcu102
adi_project_files fmcomms5_zcu102 [list \
"system_top.v" \
"system_constr.xdc"\
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
adi_project_run fmcomms5_zcu102

323
projects/fmcomms5/zcu102/system_top.v Normal file
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@ -0,0 +1,323 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
gpio_bd_i,
gpio_bd_o,
rx_clk_in_0_p,
rx_clk_in_0_n,
rx_frame_in_0_p,
rx_frame_in_0_n,
rx_data_in_0_p,
rx_data_in_0_n,
tx_clk_out_0_p,
tx_clk_out_0_n,
tx_frame_out_0_p,
tx_frame_out_0_n,
tx_data_out_0_p,
tx_data_out_0_n,
gpio_status_0,
gpio_ctl_0,
gpio_en_agc_0,
mcs_sync,
gpio_resetb_0,
enable_0,
txnrx_0,
gpio_debug_1_0,
gpio_debug_2_0,
gpio_calsw_1_0,
gpio_calsw_2_0,
gpio_ad5355_rfen,
gpio_ad5355_lock,
rx_clk_in_1_p,
rx_clk_in_1_n,
rx_frame_in_1_p,
rx_frame_in_1_n,
rx_data_in_1_p,
rx_data_in_1_n,
tx_clk_out_1_p,
tx_clk_out_1_n,
tx_frame_out_1_p,
tx_frame_out_1_n,
tx_data_out_1_p,
tx_data_out_1_n,
gpio_status_1,
gpio_ctl_1,
gpio_en_agc_1,
gpio_resetb_1,
enable_1,
txnrx_1,
gpio_debug_3_1,
gpio_debug_4_1,
gpio_calsw_3_1,
gpio_calsw_4_1,
spi_ad9361_0,
spi_ad9361_1,
spi_ad5355,
spi_clk,
spi_mosi,
spi_miso,
ref_clk_p,
ref_clk_n);
input [12:0] gpio_bd_i;
output [ 7:0] gpio_bd_o;
input rx_clk_in_0_p;
input rx_clk_in_0_n;
input rx_frame_in_0_p;
input rx_frame_in_0_n;
input [ 5:0] rx_data_in_0_p;
input [ 5:0] rx_data_in_0_n;
output tx_clk_out_0_p;
output tx_clk_out_0_n;
output tx_frame_out_0_p;
output tx_frame_out_0_n;
output [ 5:0] tx_data_out_0_p;
output [ 5:0] tx_data_out_0_n;
input [ 7:0] gpio_status_0;
output [ 3:0] gpio_ctl_0;
output gpio_en_agc_0;
output mcs_sync;
output gpio_resetb_0;
output enable_0;
output txnrx_0;
output gpio_debug_1_0;
output gpio_debug_2_0;
output gpio_calsw_1_0;
output gpio_calsw_2_0;
output gpio_ad5355_rfen;
input gpio_ad5355_lock;
input rx_clk_in_1_p;
input rx_clk_in_1_n;
input rx_frame_in_1_p;
input rx_frame_in_1_n;
input [ 5:0] rx_data_in_1_p;
input [ 5:0] rx_data_in_1_n;
output tx_clk_out_1_p;
output tx_clk_out_1_n;
output tx_frame_out_1_p;
output tx_frame_out_1_n;
output [ 5:0] tx_data_out_1_p;
output [ 5:0] tx_data_out_1_n;
input [ 7:0] gpio_status_1;
output [ 3:0] gpio_ctl_1;
output gpio_en_agc_1;
output gpio_resetb_1;
output enable_1;
output txnrx_1;
output gpio_debug_3_1;
output gpio_debug_4_1;
output gpio_calsw_3_1;
output gpio_calsw_4_1;
output spi_ad9361_0;
output spi_ad9361_1;
output spi_ad5355;
output spi_clk;
output spi_mosi;
input spi_miso;
input ref_clk_p;
input ref_clk_n;
// internal registers
reg [ 2:0] mcs_sync_m = 'd0;
reg mcs_sync = 'd0;
// internal signals
wire sys_100m_resetn;
wire ref_clk_s;
wire ref_clk;
wire [ 94:0] gpio_i;
wire [ 94:0] gpio_o;
wire gpio_sync;
wire gpio_open_44_44;
wire gpio_open_15_15;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire txnrx_0;
wire enable_0;
wire txnrx_1;
wire enable_1;
// multi-chip synchronization
always @(posedge ref_clk or negedge sys_100m_resetn) begin
if (sys_100m_resetn == 1'b0) begin
mcs_sync_m <= 3'd0;
mcs_sync <= 1'd0;
end else begin
mcs_sync_m <= {mcs_sync_m[1:0], gpio_sync};
mcs_sync <= mcs_sync_m[2] & ~mcs_sync_m[1];
end
end
// instantiations
IBUFGDS i_ref_clk_ibuf (
.I (ref_clk_p),
.IB (ref_clk_n),
.O (ref_clk_s));
BUFR #(.BUFR_DIVIDE("BYPASS")) i_ref_clk_rbuf (
.CLR (1'b0),
.CE (1'b1),
.I (ref_clk_s),
.O (ref_clk));
assign gpio_resetb_1 = gpio_o[65];
assign gpio_i[64] = gpio_ad5355_lock;
assign gpio_ad5355_rfen = gpio_o[63];
assign gpio_calsw_4_1 = gpio_o[62];
assign gpio_calsw_3_1 = gpio_o[61];
assign gpio_calsw_2_0 = gpio_o[60];
assign gpio_calsw_1_0 = gpio_o[59];
assign gpio_txnrx_1 = gpio_o[58];
assign gpio_enable_1 = gpio_o[57];
assign gpio_en_agc_1 = gpio_o[56];
assign gpio_txnrx_0 = gpio_o[55];
assign gpio_enable_0 = gpio_o[54];
assign gpio_en_agc_0 = gpio_o[53];
assign gpio_resetb_0 = gpio_o[52];
assign gpio_sync = gpio_o[51];
assign gpio_open_44_44 = gpio_o[50];
assign gpio_debug_4_0 = gpio_o[49];
assign gpio_debug_3_0 = gpio_o[48];
assign gpio_debug_2_0 = gpio_o[47];
assign gpio_debug_1_0 = gpio_o[46];
assign gpio_ctl_1 = gpio_o[45:42];
assign gpio_ctl_0 = gpio_o[41:38];
assign gpio_i[37:30] = gpio_status_1;
assign gpio_i[29:22] = gpio_status_0;
assign gpio_open_15_15 = gpio_o[21];
assign gpio_bd_o = gpio_o[20:13];
assign gpio_i[12: 0] = gpio_bd_i;
assign gpio_i[94:65] = gpio_o[94:65];
assign gpio_i[63:38] = gpio_o[63:38];
assign gpio_i[21:14] = gpio_o[21:14];
assign spi_ad9361_0 = spi0_csn[0];
assign spi_ad9361_1 = spi0_csn[1];
assign spi_ad5355 = spi0_csn[2];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
assign spi1_miso = 1'b0;
system_wrapper i_system_wrapper (
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_14 (1'b0),
.ps_intr_15 (1'b0),
.rx_clk_in_0_n (rx_clk_in_0_n),
.rx_clk_in_0_p (rx_clk_in_0_p),
.rx_clk_in_1_n (rx_clk_in_1_n),
.rx_clk_in_1_p (rx_clk_in_1_p),
.rx_data_in_0_n (rx_data_in_0_n),
.rx_data_in_0_p (rx_data_in_0_p),
.rx_data_in_1_n (rx_data_in_1_n),
.rx_data_in_1_p (rx_data_in_1_p),
.rx_frame_in_0_n (rx_frame_in_0_n),
.rx_frame_in_0_p (rx_frame_in_0_p),
.rx_frame_in_1_n (rx_frame_in_1_n),
.rx_frame_in_1_p (rx_frame_in_1_p),
.spi0_csn (spi0_csn),
.spi0_miso (spi0_miso),
.spi0_mosi (spi0_mosi),
.spi0_sclk (spi0_clk),
.spi1_csn (spi1_csn),
.spi1_miso (spi1_miso),
.spi1_mosi (spi1_mosi),
.spi1_sclk (spi1_clk),
.sys_100m_resetn (sys_100m_resetn),
.tx_clk_out_0_n (tx_clk_out_0_n),
.tx_clk_out_0_p (tx_clk_out_0_p),
.tx_clk_out_1_n (tx_clk_out_1_n),
.tx_clk_out_1_p (tx_clk_out_1_p),
.tx_data_out_0_n (tx_data_out_0_n),
.tx_data_out_0_p (tx_data_out_0_p),
.tx_data_out_1_n (tx_data_out_1_n),
.tx_data_out_1_p (tx_data_out_1_p),
.tx_frame_out_0_n (tx_frame_out_0_n),
.tx_frame_out_0_p (tx_frame_out_0_p),
.tx_frame_out_1_n (tx_frame_out_1_n),
.tx_frame_out_1_p (tx_frame_out_1_p),
.txnrx_0 (txnrx_0),
.enable_0 (enable_0),
.up_enable_0 (gpio_enable_0),
.up_txnrx_0 (gpio_txnrx_0),
.txnrx_1 (txnrx_1),
.enable_1 (enable_1),
.up_enable_1 (gpio_enable_1),
.up_txnrx_1 (gpio_txnrx_1));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/pzsdr1/ccbox_lvds/Makefile
View File

@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_i2s_adi
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/pzsdr1/ccbrk_cmos/Makefile
View File

@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_gpreg clean make -C ../../../library/axi_gpreg clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_gpreg make -C ../../../library/axi_gpreg
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

3
projects/pzsdr1/ccbrk_cmos/system_bd.tcl
View File

@ -2,5 +2,8 @@
source ../common/pzsdr1_bd.tcl source ../common/pzsdr1_bd.tcl
source ../common/ccbrk_bd.tcl source ../common/ccbrk_bd.tcl
set_property -dict [list CONFIG.SEL_0_DIV {2}] $clkdiv
set_property -dict [list CONFIG.SEL_1_DIV {1}] $clkdiv
cfg_ad9361_interface CMOS cfg_ad9361_interface CMOS

6
projects/pzsdr1/ccbrk_lvds/Makefile
View File

@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_gpreg clean make -C ../../../library/axi_gpreg clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_gpreg make -C ../../../library/axi_gpreg
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/pzsdr1/ccusb_lvds/Makefile
View File

@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_usb_fx3 clean make -C ../../../library/axi_usb_fx3 clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_usb_fx3 make -C ../../../library/axi_usb_fx3
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

78
projects/pzsdr1/common/pzsdr1_bd.tcl
View File

@ -242,6 +242,21 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync] set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
# connections # connections
ad_connect sys_200m_clk axi_ad9361/delay_clk ad_connect sys_200m_clk axi_ad9361/delay_clk
@ -253,11 +268,14 @@ ad_connect up_enable axi_ad9361/up_enable
ad_connect up_txnrx axi_ad9361/up_txnrx ad_connect up_txnrx axi_ad9361/up_txnrx
ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk ad_connect axi_ad9361_clk clkdiv/clk
ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out
ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
@ -287,23 +305,43 @@ ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk ad_connect axi_ad9361/adc_r1_mode concat_logic/In0
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk ad_connect axi_ad9361/dac_r1_mode concat_logic/In1
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0 ad_connect concat_logic/dout clkdiv_sel_logic/Op1
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0 ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf
ad_connect dac_fifo/din_clk clkdiv/clk_out
ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
ad_connect axi_ad9361_clk dac_fifo/dout_clk
ad_connect dac_fifo/dout_rst axi_ad9361/rst
ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out
ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
ad_connect dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0
ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
ad_connect dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1
ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
ad_connect dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2
ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
ad_connect dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3
ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
ad_connect axi_ad9361/dac_data_i0 dac_fifo/dout_data_0
ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
ad_connect axi_ad9361/dac_data_q0 dac_fifo/dout_data_1
ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
ad_connect axi_ad9361/dac_data_i1 dac_fifo/dout_data_2
ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
ad_connect axi_ad9361/dac_data_q1 dac_fifo/dout_data_3
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync

6
projects/pzsdr2/ccbox_lvds/Makefile
View File

@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_i2s_adi
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/pzsdr2/ccbrk_cmos/Makefile
View File

@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -57,7 +59,9 @@ clean-all:clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_gpreg clean make -C ../../../library/axi_gpreg clean
make -C ../../../library/xilinx/axi_xcvrlb clean make -C ../../../library/xilinx/axi_xcvrlb clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -73,7 +77,9 @@ lib:
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_gpreg make -C ../../../library/axi_gpreg
make -C ../../../library/xilinx/axi_xcvrlb make -C ../../../library/xilinx/axi_xcvrlb
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

3
projects/pzsdr2/ccbrk_cmos/system_bd.tcl
View File

@ -2,5 +2,8 @@
source ../common/pzsdr2_bd.tcl source ../common/pzsdr2_bd.tcl
source ../common/ccbrk_bd.tcl source ../common/ccbrk_bd.tcl
set_property -dict [list CONFIG.SEL_0_DIV {2}] $clkdiv
set_property -dict [list CONFIG.SEL_1_DIV {1}] $clkdiv
cfg_ad9361_interface CMOS cfg_ad9361_interface CMOS

6
projects/pzsdr2/ccbrk_lvds/Makefile
View File

@ -21,7 +21,9 @@ M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -57,7 +59,9 @@ clean-all:clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_gpreg clean make -C ../../../library/axi_gpreg clean
make -C ../../../library/xilinx/axi_xcvrlb clean make -C ../../../library/xilinx/axi_xcvrlb clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -73,7 +77,9 @@ lib:
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_gpreg make -C ../../../library/axi_gpreg
make -C ../../../library/xilinx/axi_xcvrlb make -C ../../../library/xilinx/axi_xcvrlb
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/pzsdr2/ccfmc_lvds/Makefile
View File

@ -25,7 +25,9 @@ M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -65,7 +67,9 @@ clean-all:clean
make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/xilinx/axi_xcvrlb clean make -C ../../../library/xilinx/axi_xcvrlb clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -85,7 +89,9 @@ lib:
make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_i2s_adi
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/xilinx/axi_xcvrlb make -C ../../../library/xilinx/axi_xcvrlb
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/pzsdr2/ccpci_lvds/Makefile
View File

@ -19,7 +19,9 @@ M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -53,7 +55,9 @@ clean:
clean-all:clean clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -67,7 +71,9 @@ pzsdr2_ccpci_lvds.sdk/system_top.hdf: $(M_DEPS)
lib: lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

6
projects/pzsdr2/ccusb_lvds/Makefile
View File

@ -20,7 +20,9 @@ M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr M_DEPS += ../../../library/axi_ad9361/axi_ad9361.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr M_DEPS += ../../../library/axi_usb_fx3/axi_usb_fx3.xpr
M_DEPS += ../../../library/util_clkdiv/util_clkdiv.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_rfifo/util_rfifo.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -55,7 +57,9 @@ clean-all:clean
make -C ../../../library/axi_ad9361 clean make -C ../../../library/axi_ad9361 clean
make -C ../../../library/axi_dmac clean make -C ../../../library/axi_dmac clean
make -C ../../../library/axi_usb_fx3 clean make -C ../../../library/axi_usb_fx3 clean
make -C ../../../library/util_clkdiv clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_rfifo clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -70,7 +74,9 @@ lib:
make -C ../../../library/axi_ad9361 make -C ../../../library/axi_ad9361
make -C ../../../library/axi_dmac make -C ../../../library/axi_dmac
make -C ../../../library/axi_usb_fx3 make -C ../../../library/axi_usb_fx3
make -C ../../../library/util_clkdiv
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_rfifo
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

80
projects/pzsdr2/common/pzsdr2_bd.tcl
View File

@ -242,6 +242,21 @@ set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $util_ad9361_adc_fifo
set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync] set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
set_property -dict [list CONFIG.C_SIZE {2}] $clkdiv_sel_logic
set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
set_property -dict [list CONFIG.NUM_PORTS {2}] $concat_logic
# connections # connections
ad_connect sys_200m_clk axi_ad9361/delay_clk ad_connect sys_200m_clk axi_ad9361/delay_clk
@ -253,11 +268,14 @@ ad_connect up_enable axi_ad9361/up_enable
ad_connect up_txnrx axi_ad9361/up_txnrx ad_connect up_txnrx axi_ad9361/up_txnrx
ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk ad_connect axi_ad9361_clk util_ad9361_adc_fifo/din_clk
ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst ad_connect axi_ad9361/rst util_ad9361_adc_fifo/din_rst
ad_connect sys_cpu_clk util_ad9361_adc_fifo/dout_clk ad_connect axi_ad9361_clk clkdiv/clk
ad_connect sys_cpu_resetn util_ad9361_adc_fifo/dout_rstn ad_connect clkdiv/clk_out axi_ad9361_adc_dma/fifo_wr_clk
ad_connect sys_cpu_clk util_ad9361_adc_pack/adc_clk ad_connect clkdiv/clk_out util_ad9361_adc_fifo/dout_clk
ad_connect sys_cpu_reset util_ad9361_adc_pack/adc_rst ad_connect clkdiv/clk_out util_ad9361_adc_pack/adc_clk
ad_connect sys_cpu_clk axi_ad9361_adc_dma/fifo_wr_clk ad_connect clkdiv_reset/ext_reset_in sys_rstgen/peripheral_aresetn
ad_connect clkdiv_reset/slowest_sync_clk clkdiv/clk_out
ad_connect util_ad9361_adc_pack/adc_rst clkdiv_reset/peripheral_reset
ad_connect util_ad9361_adc_fifo/dout_rstn clkdiv_reset/peripheral_aresetn
ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0 ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_fifo/din_enable_0
ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0 ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_fifo/din_valid_0
ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0 ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_fifo/din_data_0
@ -287,23 +305,43 @@ ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync
ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din
ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf ad_connect axi_ad9361_adc_dma/fifo_wr_overflow util_ad9361_adc_fifo/dout_ovf
ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf ad_connect util_ad9361_adc_fifo/din_ovf axi_ad9361/adc_dovf
ad_connect axi_ad9361_clk util_ad9361_dac_upack/dac_clk ad_connect axi_ad9361/adc_r1_mode concat_logic/In0
ad_connect axi_ad9361_clk axi_ad9361_dac_dma/fifo_rd_clk ad_connect axi_ad9361/dac_r1_mode concat_logic/In1
ad_connect util_ad9361_dac_upack/dac_enable_0 axi_ad9361/dac_enable_i0 ad_connect concat_logic/dout clkdiv_sel_logic/Op1
ad_connect util_ad9361_dac_upack/dac_valid_0 axi_ad9361/dac_valid_i0 ad_connect clkdiv/clk_sel clkdiv_sel_logic/Res
ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0
ad_connect util_ad9361_dac_upack/dac_enable_1 axi_ad9361/dac_enable_q0
ad_connect util_ad9361_dac_upack/dac_valid_1 axi_ad9361/dac_valid_q0
ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0
ad_connect util_ad9361_dac_upack/dac_enable_2 axi_ad9361/dac_enable_i1
ad_connect util_ad9361_dac_upack/dac_valid_2 axi_ad9361/dac_valid_i1
ad_connect util_ad9361_dac_upack/dac_data_2 axi_ad9361/dac_data_i1
ad_connect util_ad9361_dac_upack/dac_enable_3 axi_ad9361/dac_enable_q1
ad_connect util_ad9361_dac_upack/dac_valid_3 axi_ad9361/dac_valid_q1
ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf ad_connect clkdiv/clk_out axi_ad9361_dac_dma/fifo_rd_clk
ad_connect axi_ad9361/dac_dunf dac_fifo/dout_unf
ad_connect dac_fifo/din_clk clkdiv/clk_out
ad_connect dac_fifo/din_rstn clkdiv_reset/peripheral_aresetn
ad_connect axi_ad9361_clk dac_fifo/dout_clk
ad_connect dac_fifo/dout_rst axi_ad9361/rst
ad_connect util_ad9361_dac_upack/dac_clk clkdiv/clk_out
ad_connect dac_fifo/din_enable_0 util_ad9361_dac_upack/dac_enable_0
ad_connect dac_fifo/din_valid_0 util_ad9361_dac_upack/dac_valid_0
ad_connect dac_fifo/din_data_0 util_ad9361_dac_upack/dac_data_0
ad_connect dac_fifo/din_enable_1 util_ad9361_dac_upack/dac_enable_1
ad_connect dac_fifo/din_valid_1 util_ad9361_dac_upack/dac_valid_1
ad_connect dac_fifo/din_data_1 util_ad9361_dac_upack/dac_data_1
ad_connect dac_fifo/din_enable_2 util_ad9361_dac_upack/dac_enable_2
ad_connect dac_fifo/din_valid_2 util_ad9361_dac_upack/dac_valid_2
ad_connect dac_fifo/din_data_2 util_ad9361_dac_upack/dac_data_2
ad_connect dac_fifo/din_enable_3 util_ad9361_dac_upack/dac_enable_3
ad_connect dac_fifo/din_valid_3 util_ad9361_dac_upack/dac_valid_3
ad_connect dac_fifo/din_data_3 util_ad9361_dac_upack/dac_data_3
ad_connect axi_ad9361/dac_enable_i0 dac_fifo/dout_enable_0
ad_connect axi_ad9361/dac_valid_i0 dac_fifo/dout_valid_0
ad_connect axi_ad9361/dac_data_i0 dac_fifo/dout_data_0
ad_connect axi_ad9361/dac_enable_q0 dac_fifo/dout_enable_1
ad_connect axi_ad9361/dac_valid_q0 dac_fifo/dout_valid_1
ad_connect axi_ad9361/dac_data_q0 dac_fifo/dout_data_1
ad_connect axi_ad9361/dac_enable_i1 dac_fifo/dout_enable_2
ad_connect axi_ad9361/dac_valid_i1 dac_fifo/dout_valid_2
ad_connect axi_ad9361/dac_data_i1 dac_fifo/dout_data_2
ad_connect axi_ad9361/dac_enable_q1 dac_fifo/dout_enable_3
ad_connect axi_ad9361/dac_valid_q1 dac_fifo/dout_valid_3
ad_connect axi_ad9361/dac_data_q1 dac_fifo/dout_data_3
ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
@ -334,7 +372,7 @@ ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
## 2R2T supports 1R1T as a run time option. ## 2R2T supports 1R1T as a run time option.
## 1R1T allows core to run at a lower rate (1/2 of 2R2T) ## 1R1T allows core to run at a lower rate (1/2 of 2R2T)
set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361] set_property CONFIG.MODE_1R1T 0 [get_bd_cells axi_ad9361]
## interface type - CMOS (1) or LVDS (0) (default is LVDS) ## interface type - CMOS (1) or LVDS (0) (default is LVDS)
## CMOS allows core to run at a lower rate (1/2 of LVDS) ## CMOS allows core to run at a lower rate (1/2 of LVDS)