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library/axi_dacfifo: Fix reset for a few registers

main
Istvan Csomortani 2016-06-15 12:23:38 +03:00
parent 10090a296e
commit d5ce137c55
1 changed files with 2 additions and 0 deletions
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2
library/axi_dacfifo/axi_dacfifo_wr.v
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@ -344,6 +344,7 @@ module axi_dacfifo_wr (
dma_mem_raddr_m1 <= 'b0;
dma_mem_raddr_m2 <= 'b0;
dma_mem_raddr <= 'b0;
dma_ready <= 1'b0;
end else begin
dma_mem_raddr_m1 <= axi_mem_raddr_g;
dma_mem_raddr_m2 <= dma_mem_raddr_m1;
@ -448,6 +449,7 @@ module axi_dacfifo_wr (
axi_mem_raddr <= 'b0;
axi_wvalid_counter <= 4'b0;
axi_mem_last_read_toggle <= 1'b1;
axi_mem_raddr_g <= 8'b0;
end else begin
axi_mem_rvalid <= axi_mem_rvalid_s;
axi_mem_rvalid_d <= axi_mem_rvalid;