axi_ad7616: Fix the register map
parent
2ccdd426ec
commit
d5d7c12f0e
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@ -124,8 +124,8 @@ module axi_ad7616_control (
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wire up_rst;
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wire up_rreq_s;
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wire up_rack_s;
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wire up_wreq_s;
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wire end_of_conv_s;
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wire [31:0] up_read_data_s;
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wire up_read_valid_s;
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@ -138,7 +138,7 @@ module axi_ad7616_control (
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// the up_[read/write]_data interfaces are valid just in parallel mode
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assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
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assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : 32'hDEAD;
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assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
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// processor write interface
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@ -175,21 +175,23 @@ module axi_ad7616_control (
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// processor read interface
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assign up_rack_s = (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 1'b0;
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up_rdata <= 32'b0;
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end else begin
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up_rack <= (up_raddr[7:0] == 8'h13) ? up_read_valid_s : up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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up_rack <= up_rack_s;
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if (up_rack_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00 : up_rdata = PCORE_VERSION;
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8'h01 : up_rdata = ID;
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8'h02 : up_rdata = up_scratch;
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8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
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8'h11 : up_rdata = up_conv_rate;
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8'h12 : up_rdata = up_burst_length;
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8'h13 : up_rdata = up_read_data_s;
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8'h00 : up_rdata = PCORE_VERSION;
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8'h01 : up_rdata = ID;
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8'h02 : up_rdata = up_scratch;
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8'h10 : up_rdata = {29'b0, up_cnvst_en, up_resetn};
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8'h11 : up_rdata = up_conv_rate;
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8'h12 : up_rdata = {27'b0, up_burst_length};
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8'h13 : up_rdata = up_read_data_s;
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endcase
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end
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end
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@ -207,7 +209,7 @@ module axi_ad7616_control (
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.clk (up_clk),
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.rst (up_rst),
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.in (busy),
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.out (end_of_conv_s)
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.out (end_of_conv)
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);
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// convertion start generator
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@ -243,7 +245,6 @@ module axi_ad7616_control (
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end
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assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
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assign end_of_conv = end_of_conv_s;
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endmodule
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