From d6256e9e294b02fad75abf122806e9b2e9e771cd Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 10 Mar 2014 11:11:16 -0400 Subject: [PATCH] library: dds and dcfilter changes, added fifo wrappers --- library/common/ad_dds.v | 100 ++++++++++++++ library/common/ad_dds_sine.v | 195 +++++++++++++++++++++++++++ library/util_rfifo/util_rfifo.v | 142 +++++++++++++++++++ library/util_rfifo/util_rfifo_ip.tcl | 13 ++ library/util_wfifo/util_wfifo.v | 142 +++++++++++++++++++ library/util_wfifo/util_wfifo_ip.tcl | 13 ++ 6 files changed, 605 insertions(+) create mode 100644 library/common/ad_dds.v create mode 100644 library/common/ad_dds_sine.v create mode 100644 library/util_rfifo/util_rfifo.v create mode 100644 library/util_rfifo/util_rfifo_ip.tcl create mode 100644 library/util_wfifo/util_wfifo.v create mode 100644 library/util_wfifo/util_wfifo_ip.tcl diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v new file mode 100644 index 000000000..227673c43 --- /dev/null +++ b/library/common/ad_dds.v @@ -0,0 +1,100 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_dds ( + + // interface + + clk, + dds_format, + dds_phase_0, + dds_scale_0, + dds_phase_1, + dds_scale_1, + dds_data); + + // interface + + input clk; + input dds_format; + input [15:0] dds_phase_0; + input [15:0] dds_scale_0; + input [15:0] dds_phase_1; + input [15:0] dds_scale_1; + output [15:0] dds_data; + + // internal registers + + reg [15:0] dds_data_int = 'd0; + reg [15:0] dds_data = 'd0; + + // internal signals + + wire [15:0] dds_data_0_s; + wire [15:0] dds_data_1_s; + + // dds channel output + + always @(posedge clk) begin + dds_data_int <= dds_data_0_s + dds_data_1_s; + dds_data <= {(dds_format ^ dds_data_int[15]), dds_data_int[14:0]}; + end + + // dds-1 + + ad_dds_1 i_dds_1_0 ( + .clk (clk), + .angle (dds_phase_0), + .scale (dds_scale_0), + .dds_data (dds_data_0_s)); + + // dds-2 + + ad_dds_1 i_dds_1_1 ( + .clk (clk), + .angle (dds_phase_1), + .scale (dds_scale_1), + .dds_data (dds_data_1_s)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/common/ad_dds_sine.v b/library/common/ad_dds_sine.v new file mode 100644 index 000000000..431b7ccc1 --- /dev/null +++ b/library/common/ad_dds_sine.v @@ -0,0 +1,195 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// this is a sine function (approximate), the basic idea is to approximate sine as a +// polynomial function (there are a lot of stuff about this on the web) + +`timescale 1ns/100ps + +module ad_dds_sine ( + + // sine = sin(angle) + + clk, + angle, + sine, + ddata_in, + ddata_out); + + // parameters + + parameter DELAY_DATA_WIDTH = 16; + localparam DW = DELAY_DATA_WIDTH - 1; + + // sine = sin(angle) + + input clk; + input [15:0] angle; + output [15:0] sine; + input [DW:0] ddata_in; + output [DW:0] ddata_out; + + // internal registers + + reg [DW:0] ddata_s2_i = 'd0; + reg data_msb_s2_i = 'd0; + reg [15:0] data_delay_s2_i = 'd0; + reg [15:0] data_sine_s2_i = 'd0; + reg [DW:0] ddata_s2 = 'd0; + reg data_msb_s2 = 'd0; + reg [15:0] data_sine_s2 = 'd0; + reg [DW:0] ddata_s3_i = 'd0; + reg data_msb_s3_i = 'd0; + reg [15:0] data_delay_s3_i = 'd0; + reg [15:0] data_sine_s3_i = 'd0; + reg [DW:0] ddata_s4 = 'd0; + reg data_msb = 'd0; + reg [14:0] data_sine_p = 'd0; + reg [14:0] data_sine_n = 'd0; + reg [DW:0] ddata_out = 'd0; + reg [15:0] sine = 'd0; + + // internal signals + + wire [DW:0] ddata_s1_s; + wire data_msb_s1_s; + wire [31:0] data_sine_s1_s; + wire [DW:0] ddata_s2_i_s; + wire data_msb_s2_i_s; + wire [15:0] data_delay_s2_i_s; + wire [31:0] data_sine_s2_i_s; + wire [DW:0] ddata_s2_s; + wire data_msb_s2_s; + wire [31:0] data_sine_s2_s; + wire [DW:0] ddata_s3_i_s; + wire data_msb_s3_i_s; + wire [15:0] data_delay_s3_i_s; + wire [31:0] data_sine_s3_i_s; + wire [DW:0] ddata_s3_s; + wire data_msb_s3_s; + wire [31:0] data_sine_s3_s; + + // level 1 (intermediate) A*x; + + ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s1 ( + .clk (clk), + .data_a ({1'b0, angle[14:0]}), + .data_b (16'hc90f), + .data_p (data_sine_s1_s), + .ddata_in ({ddata_in, angle[15]}), + .ddata_out ({ddata_s1_s, data_msb_s1_s})); + + // level 1, (final) B*x; + + ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2_i ( + .clk (clk), + .data_a (data_sine_s1_s[30:15]), + .data_b (16'h19f0), + .data_p (data_sine_s2_i_s), + .ddata_in ({ddata_s1_s, data_msb_s1_s, data_sine_s1_s[30:15]}), + .ddata_out ({ddata_s2_i_s, data_msb_s2_i_s, data_delay_s2_i_s})); + + // level 2 inputs, B*x and (1-A*x) + + always @(posedge clk) begin + ddata_s2_i <= ddata_s2_i_s; + data_msb_s2_i <= data_msb_s2_i_s; + data_delay_s2_i <= data_delay_s2_i_s; + data_sine_s2_i <= 16'ha2f9 - data_sine_s2_i_s[28:13]; + end + + // level 2, second order (A*x2 + B*x) + + ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s2 ( + .clk (clk), + .data_a (data_delay_s2_i), + .data_b (data_sine_s2_i), + .data_p (data_sine_s2_s), + .ddata_in ({ddata_s2_i, data_msb_s2_i}), + .ddata_out ({ddata_s2_s, data_msb_s2_s})); + + always @(posedge clk) begin + ddata_s2 <= ddata_s2_s; + data_msb_s2 <= data_msb_s2_s; + if (data_sine_s2_s[31:29] == 0) begin + data_sine_s2 <= data_sine_s2_s[28:13]; + end else begin + data_sine_s2 <= 16'hffff; + end + end + + // level 2, intermediate (B*y) + + ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s3_i ( + .clk (clk), + .data_a (data_sine_s2), + .data_b (16'h3999), + .data_p (data_sine_s3_i_s), + .ddata_in ({ddata_s2, data_msb_s2, data_sine_s2}), + .ddata_out ({ddata_s3_i_s, data_msb_s3_i_s, data_delay_s3_i_s})); + + always @(posedge clk) begin + ddata_s3_i <= ddata_s3_i_s; + data_msb_s3_i <= data_msb_s3_i_s; + data_delay_s3_i <= data_delay_s3_i_s; + data_sine_s3_i <= 16'hc666 + data_sine_s3_i_s[31:16]; + end + + // level 2, second order (A*y2 + B*y) + + ad_mul_u16 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+1)) i_mul_s3 ( + .clk (clk), + .data_a (data_delay_s3_i), + .data_b (data_sine_s3_i), + .data_p (data_sine_s3_s), + .ddata_in ({ddata_s3_i, data_msb_s3_i}), + .ddata_out ({ddata_s3_s, data_msb_s3_s})); + + always @(posedge clk) begin + ddata_s4 <= ddata_s3_s; + data_msb <= data_msb_s3_s; + data_sine_p <= data_sine_s3_s[31:17]; + data_sine_n <= ~data_sine_s3_s[31:17] + 1'b1; + ddata_out <= ddata_s4; + sine <= (data_msb == 1'b1) ? {1'b1, data_sine_n} : {1'b0, data_sine_p}; + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/util_rfifo/util_rfifo.v b/library/util_rfifo/util_rfifo.v new file mode 100644 index 000000000..8c1195cd4 --- /dev/null +++ b/library/util_rfifo/util_rfifo.v @@ -0,0 +1,142 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_wfifo ( + + rstn, + clk, + + src_wr, + src_wdata, + src_wovf, + dst_wr, + dst_wdata, + dst_wovf, + + fifo_rst, + fifo_wr, + fifo_wdata, + fifo_wfull, + fifo_wovf, + fifo_rd, + fifo_rdata, + fifo_rempty); + + // parameters (read (S) bus width must be greater than write (M)) + + parameter SRC_DATA_WIDTH = 32; + parameter DST_DATA_WIDTH = 64; + + // common clock + + input rstn; + input clk; + + // master/slave write + + input src_wr; + input [SRC_DATA_WIDTH-1:0] src_wdata; + output src_wovf; + output dst_wr; + output [DST_DATA_WIDTH-1:0] dst_wdata; + input dst_wovf; + + // fifo interface + + output fifo_rst; + output fifo_wr; + output [SRC_DATA_WIDTH-1:0] fifo_wdata; + input fifo_wfull; + input fifo_wovf; + output fifo_rd; + input [DST_DATA_WIDTH-1:0] fifo_rdata; + input fifo_rempty; + + // internal registers + + reg fifo_rst = 'd0; + reg src_wovf = 'd0; + reg dst_wr = 'd0; + + // defaults + + always @(posedge clk or negedge rstn) begin + if (rstn == 1'b0) begin + fifo_rst <= 1'b1; + end else begin + fifo_rst <= 1'b0; + end + end + + // write is pass through (fifo can never become full nor overflow) + + assign fifo_wr = src_wr; + + genvar m; + generate + for (m = 0; m < SRC_DATA_WIDTH; m = m + 1) begin: g_wdata + assign fifo_wdata[m] = src_wdata[(SRC_DATA_WIDTH-1)-m]; + end + endgenerate + + always @(posedge clk) begin + src_wovf <= dst_wovf | fifo_wfull | fifo_wovf; + end + + // read is non-destructive + + assign fifo_rd = ~fifo_rempty; + + always @(posedge clk) begin + dst_wr <= fifo_rd; + end + + genvar s; + generate + for (s = 0; s < DST_DATA_WIDTH; s = s + 1) begin: g_rdata + assign dst_wdata[s] = fifo_rdata[(DST_DATA_WIDTH-1)-s]; + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/util_rfifo/util_rfifo_ip.tcl b/library/util_rfifo/util_rfifo_ip.tcl new file mode 100644 index 000000000..a84c33d3b --- /dev/null +++ b/library/util_rfifo/util_rfifo_ip.tcl @@ -0,0 +1,13 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_wfifo +adi_ip_files util_wfifo [list \ + "util_wfifo.v" ] + +adi_ip_properties_lite util_wfifo +ipx::save_core [ipx::current_core] + + diff --git a/library/util_wfifo/util_wfifo.v b/library/util_wfifo/util_wfifo.v new file mode 100644 index 000000000..8c1195cd4 --- /dev/null +++ b/library/util_wfifo/util_wfifo.v @@ -0,0 +1,142 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_wfifo ( + + rstn, + clk, + + src_wr, + src_wdata, + src_wovf, + dst_wr, + dst_wdata, + dst_wovf, + + fifo_rst, + fifo_wr, + fifo_wdata, + fifo_wfull, + fifo_wovf, + fifo_rd, + fifo_rdata, + fifo_rempty); + + // parameters (read (S) bus width must be greater than write (M)) + + parameter SRC_DATA_WIDTH = 32; + parameter DST_DATA_WIDTH = 64; + + // common clock + + input rstn; + input clk; + + // master/slave write + + input src_wr; + input [SRC_DATA_WIDTH-1:0] src_wdata; + output src_wovf; + output dst_wr; + output [DST_DATA_WIDTH-1:0] dst_wdata; + input dst_wovf; + + // fifo interface + + output fifo_rst; + output fifo_wr; + output [SRC_DATA_WIDTH-1:0] fifo_wdata; + input fifo_wfull; + input fifo_wovf; + output fifo_rd; + input [DST_DATA_WIDTH-1:0] fifo_rdata; + input fifo_rempty; + + // internal registers + + reg fifo_rst = 'd0; + reg src_wovf = 'd0; + reg dst_wr = 'd0; + + // defaults + + always @(posedge clk or negedge rstn) begin + if (rstn == 1'b0) begin + fifo_rst <= 1'b1; + end else begin + fifo_rst <= 1'b0; + end + end + + // write is pass through (fifo can never become full nor overflow) + + assign fifo_wr = src_wr; + + genvar m; + generate + for (m = 0; m < SRC_DATA_WIDTH; m = m + 1) begin: g_wdata + assign fifo_wdata[m] = src_wdata[(SRC_DATA_WIDTH-1)-m]; + end + endgenerate + + always @(posedge clk) begin + src_wovf <= dst_wovf | fifo_wfull | fifo_wovf; + end + + // read is non-destructive + + assign fifo_rd = ~fifo_rempty; + + always @(posedge clk) begin + dst_wr <= fifo_rd; + end + + genvar s; + generate + for (s = 0; s < DST_DATA_WIDTH; s = s + 1) begin: g_rdata + assign dst_wdata[s] = fifo_rdata[(DST_DATA_WIDTH-1)-s]; + end + endgenerate + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/library/util_wfifo/util_wfifo_ip.tcl b/library/util_wfifo/util_wfifo_ip.tcl new file mode 100644 index 000000000..a84c33d3b --- /dev/null +++ b/library/util_wfifo/util_wfifo_ip.tcl @@ -0,0 +1,13 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_wfifo +adi_ip_files util_wfifo [list \ + "util_wfifo.v" ] + +adi_ip_properties_lite util_wfifo +ipx::save_core [ipx::current_core] + +