diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index 7424ec3eb..52a442b35 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -1,48 +1,19 @@ -# ad6676 - -create_bd_port -dir I rx_ref_clk -create_bd_port -dir O rx_sync -create_bd_port -dir O rx_sysref -create_bd_port -dir I -from 1 -to 0 rx_data_p -create_bd_port -dir I -from 1 -to 0 rx_data_n - # adc peripherals -set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] +set axi_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad6676_xcvr] +set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_xcvr +set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad6676_xcvr +set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad6676_xcvr set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad6676_jesd] set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd -set axi_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad6676_gt] -set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad6676_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad6676_gt -set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_0 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_0 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad6676_gt -set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CLK25_DIV_1 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.TX_CLK25_DIV_1 {13}] $axi_ad6676_gt -set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad6676_gt -set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad6676_gt +set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core] -set util_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad6676_gt] -set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad6676_gt -set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad6676_gt -set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad6676_gt -set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad6676_gt -set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_gt -set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad6676_gt +set axi_ad6676_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad6676_cpack] +set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad6676_cpack set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad6676_dma @@ -57,71 +28,47 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma -set adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 adc_pack] -set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $adc_pack +# transceiver core -# connections (gt) +set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr] +set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr +set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr -ad_connect util_ad6676_gt/qpll_ref_clk rx_ref_clk -ad_connect util_ad6676_gt/cpll_ref_clk rx_ref_clk - -ad_connect axi_ad6676_gt/gt_pll_0 util_ad6676_gt/gt_pll_0 -ad_connect axi_ad6676_gt/gt_pll_1 util_ad6676_gt/gt_pll_1 - -ad_connect axi_ad6676_gt/gt_rx_0 util_ad6676_gt/gt_rx_0 -ad_connect axi_ad6676_gt/gt_rx_1 util_ad6676_gt/gt_rx_1 - -ad_connect axi_ad6676_gt/gt_rx_ip_0 axi_ad6676_jesd/gt0_rx -ad_connect axi_ad6676_gt/gt_rx_ip_1 axi_ad6676_jesd/gt1_rx - -ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_0 axi_ad6676_jesd/rxencommaalign_out -ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_1 axi_ad6676_jesd/rxencommaalign_out +ad_connect sys_cpu_resetn util_ad6676_xcvr/up_rstn +ad_connect sys_cpu_clk util_ad6676_xcvr/up_clk # connections (adc) -ad_connect util_ad6676_gt/rx_p rx_data_p -ad_connect util_ad6676_gt/rx_n rx_data_n -ad_connect util_ad6676_gt/rx_sync rx_sync -ad_connect util_ad6676_gt/rx_ip_sysref rx_sysref +ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd +ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk +ad_connect axi_ad6676_jesd/rx_start_of_frame axi_ad6676_core/rx_sof +ad_connect axi_ad6676_jesd/rx_tdata axi_ad6676_core/rx_data +ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk +ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/adc_rst +ad_connect axi_ad6676_core/adc_enable_0 axi_ad6676_cpack/adc_enable_0 +ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/adc_valid_0 +ad_connect axi_ad6676_core/adc_data_0 axi_ad6676_cpack/adc_data_0 +ad_connect axi_ad6676_core/adc_enable_1 axi_ad6676_cpack/adc_enable_1 +ad_connect axi_ad6676_core/adc_valid_1 axi_ad6676_cpack/adc_valid_1 +ad_connect axi_ad6676_core/adc_data_1 axi_ad6676_cpack/adc_data_1 -ad_connect util_ad6676_gt/rx_out_clk util_ad6676_gt/rx_clk -ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_jesd/rx_core_clk -ad_connect util_ad6676_gt/rx_ip_rst axi_ad6676_jesd/rx_reset -ad_connect util_ad6676_gt/rx_ip_rst_done axi_ad6676_jesd/rx_reset_done -ad_connect util_ad6676_gt/rx_ip_sysref axi_ad6676_jesd/rx_sysref -ad_connect util_ad6676_gt/rx_ip_sync axi_ad6676_jesd/rx_sync -ad_connect util_ad6676_gt/rx_ip_sof axi_ad6676_jesd/rx_start_of_frame -ad_connect util_ad6676_gt/rx_ip_data axi_ad6676_jesd/rx_tdata - -ad_connect axi_ad6676_core/adc_clk adc_pack/adc_clk -ad_connect axi_ad6676_core/adc_rst adc_pack/adc_rst -ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_core/rx_clk -ad_connect util_ad6676_gt/rx_data axi_ad6676_core/rx_data - -ad_connect axi_ad6676_core/adc_enable_a adc_pack/adc_enable_0 -ad_connect axi_ad6676_core/adc_valid_a adc_pack/adc_valid_0 -ad_connect axi_ad6676_core/adc_data_a adc_pack/adc_data_0 -ad_connect axi_ad6676_core/adc_enable_b adc_pack/adc_enable_1 -ad_connect axi_ad6676_core/adc_valid_b adc_pack/adc_valid_1 -ad_connect axi_ad6676_core/adc_data_b adc_pack/adc_data_1 - -ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk -ad_connect axi_ad6676_dma/fifo_wr_en adc_pack/adc_valid -ad_connect axi_ad6676_dma/fifo_wr_sync adc_pack/adc_sync -ad_connect axi_ad6676_dma/fifo_wr_din adc_pack/adc_data -ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow +ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk +ad_connect axi_ad6676_dma/fifo_wr_en axi_ad6676_cpack/adc_valid +ad_connect axi_ad6676_dma/fifo_wr_sync axi_ad6676_cpack/adc_sync +ad_connect axi_ad6676_dma/fifo_wr_din axi_ad6676_cpack/adc_data +ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow # interconnect (cpu) -ad_cpu_interconnect 0x44A60000 axi_ad6676_gt +ad_cpu_interconnect 0x44A60000 axi_ad6676_xcvr ad_cpu_interconnect 0x44A10000 axi_ad6676_core ad_cpu_interconnect 0x44A91000 axi_ad6676_jesd ad_cpu_interconnect 0x7c420000 axi_ad6676_dma -# gt uses hp3, and 100MHz clock for both DRP and AXI4 +# xcvr uses hp3, and 100MHz clock for both DRP and AXI4 ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_gt/m_axi +ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_xcvr/m_axi # interconnect (adc) diff --git a/projects/ad6676evb/vc707/Makefile b/projects/ad6676evb/vc707/Makefile index f37c1c0ef..3ecc4452d 100644 --- a/projects/ad6676evb/vc707/Makefile +++ b/projects/ad6676evb/vc707/Makefile @@ -18,10 +18,10 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc M_DEPS += ../../common/vc707/vc707_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_VIVADO := vivado -mode batch -source @@ -51,10 +51,10 @@ clean: clean-all:clean make -C ../../../library/axi_ad6676 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_dmac clean - make -C ../../../library/axi_jesd_gt clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS) @@ -64,10 +64,10 @@ ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS) lib: make -C ../../../library/axi_ad6676 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_dmac - make -C ../../../library/axi_jesd_gt + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt #################################################################################### #################################################################################### diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc index a7ad92199..4d650e118 100644 --- a/projects/ad6676evb/vc707/system_constr.xdc +++ b/projects/ad6676evb/vc707/system_constr.xdc @@ -17,11 +17,11 @@ set_property -dict {PACKAGE_PIN H41 IOSTANDARD LVCMOS18} [get_ports spi_clk] set_property -dict {PACKAGE_PIN H40 IOSTANDARD LVCMOS18} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P set_property -dict {PACKAGE_PIN M41 IOSTANDARD LVCMOS18} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN J42 IOSTANDARD LVCMOS18} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN M37 IOSTANDARD LVCMOS18} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN G41 IOSTANDARD LVCMOS18} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN G42 IOSTANDARD LVCMOS18} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N @@ -31,4 +31,7 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4] # clocks create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + diff --git a/projects/ad6676evb/vc707/system_project.tcl b/projects/ad6676evb/vc707/system_project.tcl index 5c7821c5b..8ee83f3a3 100644 --- a/projects/ad6676evb/vc707/system_project.tcl +++ b/projects/ad6676evb/vc707/system_project.tcl @@ -12,8 +12,6 @@ adi_project_files ad6676evb_vc707 [list \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ] -set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc] - adi_project_run ad6676evb_vc707 diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v index 80dab57c3..017dd51e0 100644 --- a/projects/ad6676evb/vc707/system_top.v +++ b/projects/ad6676evb/vc707/system_top.v @@ -289,11 +289,13 @@ module system_top ( .mgt_clk_clk_p (mgt_clk_p), .phy_rstn (phy_rstn), .phy_sd (1'b1), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .sgmii_rxn (sgmii_rxn), .sgmii_rxp (sgmii_rxp), .sgmii_txn (sgmii_txn), diff --git a/projects/ad6676evb/zc706/Makefile b/projects/ad6676evb/zc706/Makefile index 149104d87..fd9ba7c07 100644 --- a/projects/ad6676evb/zc706/Makefile +++ b/projects/ad6676evb/zc706/Makefile @@ -17,13 +17,13 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc M_DEPS += ../../common/zc706/zc706_system_bd.tcl M_DEPS += ../../../library/xilinx/common/ad_iobuf.v M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr +M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr -M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr +M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr -M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr M_VIVADO := vivado -mode batch -source @@ -53,13 +53,13 @@ clean: clean-all:clean make -C ../../../library/axi_ad6676 clean + make -C ../../../library/xilinx/axi_adxcvr clean make -C ../../../library/axi_clkgen clean make -C ../../../library/axi_dmac clean make -C ../../../library/axi_hdmi_tx clean - make -C ../../../library/axi_jesd_gt clean make -C ../../../library/axi_spdif_tx clean + make -C ../../../library/xilinx/util_adxcvr clean make -C ../../../library/util_cpack clean - make -C ../../../library/util_jesd_gt clean ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS) @@ -69,13 +69,13 @@ ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS) lib: make -C ../../../library/axi_ad6676 + make -C ../../../library/xilinx/axi_adxcvr make -C ../../../library/axi_clkgen make -C ../../../library/axi_dmac make -C ../../../library/axi_hdmi_tx - make -C ../../../library/axi_jesd_gt make -C ../../../library/axi_spdif_tx + make -C ../../../library/xilinx/util_adxcvr make -C ../../../library/util_cpack - make -C ../../../library/util_jesd_gt #################################################################################### #################################################################################### diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc index 44e3a8ee7..f5d2f91db 100644 --- a/projects/ad6676evb/zc706/system_constr.xdc +++ b/projects/ad6676evb/zc706/system_constr.xdc @@ -9,26 +9,29 @@ set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G06 FMC_HPC_LA00_CC_P -set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G07 FMC_HPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G06 FMC_HPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G07 FMC_HPC_LA00_CC_N -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_agc3] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports adc_oen] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports adc_sela] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports adc_selb] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports adc_s0] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports adc_s1] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_resetb] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports adc_agc1] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports adc_agc2] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports adc_agc3] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4] ; ## G10 FMC_HPC_LA03_N # clocks create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK] +create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] + +set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] + diff --git a/projects/ad6676evb/zc706/system_project.tcl b/projects/ad6676evb/zc706/system_project.tcl index debd98e9f..22443724f 100644 --- a/projects/ad6676evb/zc706/system_project.tcl +++ b/projects/ad6676evb/zc706/system_project.tcl @@ -12,8 +12,6 @@ adi_project_files ad6676evb_zc706 [list \ "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc] - adi_project_run ad6676evb_zc706 diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v index 043fdbc68..d873226f1 100644 --- a/projects/ad6676evb/zc706/system_top.v +++ b/projects/ad6676evb/zc706/system_top.v @@ -270,11 +270,13 @@ module system_top ( .ps_intr_10 (1'b0), .ps_intr_11 (1'b0), .ps_intr_12 (1'b0), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), + .rx_data_0_n (rx_data_n[0]), + .rx_data_0_p (rx_data_p[0]), + .rx_data_1_n (rx_data_n[1]), + .rx_data_1_p (rx_data_p[1]), + .rx_ref_clk_0 (rx_ref_clk), + .rx_sync_0 (rx_sync), + .rx_sysref_0 (rx_sysref), .spdif (spdif), .spi0_clk_i (spi0_clk), .spi0_clk_o (spi0_clk),