ad6676: Update projects to xcvr frame work
Istvan Csomortani
parent
8493bd4329
commit
d6918de19e
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@ -1,48 +1,19 @@
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# ad6676
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir O rx_sync
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create_bd_port -dir O rx_sysref
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create_bd_port -dir I -from 1 -to 0 rx_data_p
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create_bd_port -dir I -from 1 -to 0 rx_data_n
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# adc peripherals
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set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
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set axi_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad6676_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad6676_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad6676_xcvr
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set axi_ad6676_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad6676_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad6676_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad6676_jesd
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set axi_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad6676_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $axi_ad6676_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_ad6676_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_0 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_0 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad6676_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_1 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_1 {13}] $axi_ad6676_gt
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set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad6676_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad6676_gt
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set axi_ad6676_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad6676:1.0 axi_ad6676_core]
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set util_ad6676_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad6676_gt]
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set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad6676_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad6676_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad6676_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad6676_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad6676_gt
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set axi_ad6676_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_ad6676_cpack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_ad6676_cpack
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set axi_ad6676_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad6676_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad6676_dma
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@ -57,71 +28,47 @@ set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad6676_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad6676_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad6676_dma
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set adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 adc_pack]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $adc_pack
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# transceiver core
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# connections (gt)
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set util_ad6676_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad6676_xcvr]
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad6676_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_ad6676_xcvr
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ad_connect util_ad6676_gt/qpll_ref_clk rx_ref_clk
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ad_connect util_ad6676_gt/cpll_ref_clk rx_ref_clk
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ad_connect axi_ad6676_gt/gt_pll_0 util_ad6676_gt/gt_pll_0
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ad_connect axi_ad6676_gt/gt_pll_1 util_ad6676_gt/gt_pll_1
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ad_connect axi_ad6676_gt/gt_rx_0 util_ad6676_gt/gt_rx_0
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ad_connect axi_ad6676_gt/gt_rx_1 util_ad6676_gt/gt_rx_1
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ad_connect axi_ad6676_gt/gt_rx_ip_0 axi_ad6676_jesd/gt0_rx
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ad_connect axi_ad6676_gt/gt_rx_ip_1 axi_ad6676_jesd/gt1_rx
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ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_0 axi_ad6676_jesd/rxencommaalign_out
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ad_connect axi_ad6676_gt/rx_gt_comma_align_enb_1 axi_ad6676_jesd/rxencommaalign_out
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ad_connect sys_cpu_resetn util_ad6676_xcvr/up_rstn
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ad_connect sys_cpu_clk util_ad6676_xcvr/up_clk
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# connections (adc)
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ad_connect util_ad6676_gt/rx_p rx_data_p
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ad_connect util_ad6676_gt/rx_n rx_data_n
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ad_connect util_ad6676_gt/rx_sync rx_sync
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ad_connect util_ad6676_gt/rx_ip_sysref rx_sysref
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ad_connect util_ad6676_gt/rx_out_clk util_ad6676_gt/rx_clk
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ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_jesd/rx_core_clk
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ad_connect util_ad6676_gt/rx_ip_rst axi_ad6676_jesd/rx_reset
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ad_connect util_ad6676_gt/rx_ip_rst_done axi_ad6676_jesd/rx_reset_done
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ad_connect util_ad6676_gt/rx_ip_sysref axi_ad6676_jesd/rx_sysref
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ad_connect util_ad6676_gt/rx_ip_sync axi_ad6676_jesd/rx_sync
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ad_connect util_ad6676_gt/rx_ip_sof axi_ad6676_jesd/rx_start_of_frame
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ad_connect util_ad6676_gt/rx_ip_data axi_ad6676_jesd/rx_tdata
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ad_connect axi_ad6676_core/adc_clk adc_pack/adc_clk
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ad_connect axi_ad6676_core/adc_rst adc_pack/adc_rst
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ad_connect util_ad6676_gt/rx_out_clk axi_ad6676_core/rx_clk
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ad_connect util_ad6676_gt/rx_data axi_ad6676_core/rx_data
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ad_connect axi_ad6676_core/adc_enable_a adc_pack/adc_enable_0
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ad_connect axi_ad6676_core/adc_valid_a adc_pack/adc_valid_0
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ad_connect axi_ad6676_core/adc_data_a adc_pack/adc_data_0
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ad_connect axi_ad6676_core/adc_enable_b adc_pack/adc_enable_1
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ad_connect axi_ad6676_core/adc_valid_b adc_pack/adc_valid_1
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ad_connect axi_ad6676_core/adc_data_b adc_pack/adc_data_1
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ad_xcvrcon util_ad6676_xcvr axi_ad6676_xcvr axi_ad6676_jesd
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ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk
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ad_connect axi_ad6676_jesd/rx_start_of_frame axi_ad6676_core/rx_sof
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ad_connect axi_ad6676_jesd/rx_tdata axi_ad6676_core/rx_data
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ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk
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ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/adc_rst
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ad_connect axi_ad6676_core/adc_enable_0 axi_ad6676_cpack/adc_enable_0
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ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/adc_valid_0
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ad_connect axi_ad6676_core/adc_data_0 axi_ad6676_cpack/adc_data_0
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ad_connect axi_ad6676_core/adc_enable_1 axi_ad6676_cpack/adc_enable_1
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ad_connect axi_ad6676_core/adc_valid_1 axi_ad6676_cpack/adc_valid_1
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ad_connect axi_ad6676_core/adc_data_1 axi_ad6676_cpack/adc_data_1
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ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk
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ad_connect axi_ad6676_dma/fifo_wr_en adc_pack/adc_valid
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ad_connect axi_ad6676_dma/fifo_wr_sync adc_pack/adc_sync
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ad_connect axi_ad6676_dma/fifo_wr_din adc_pack/adc_data
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ad_connect axi_ad6676_dma/fifo_wr_en axi_ad6676_cpack/adc_valid
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ad_connect axi_ad6676_dma/fifo_wr_sync axi_ad6676_cpack/adc_sync
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ad_connect axi_ad6676_dma/fifo_wr_din axi_ad6676_cpack/adc_data
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ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad6676_gt
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ad_cpu_interconnect 0x44A60000 axi_ad6676_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad6676_core
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ad_cpu_interconnect 0x44A91000 axi_ad6676_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad6676_dma
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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# xcvr uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_gt/m_axi
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ad_mem_hp3_interconnect sys_cpu_clk axi_ad6676_xcvr/m_axi
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# interconnect (adc)
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@ -18,10 +18,10 @@ M_DEPS += ../../common/vc707/vc707_system_constr.xdc
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M_DEPS += ../../common/vc707/vc707_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
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M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
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M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
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M_VIVADO := vivado -mode batch -source
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@ -51,10 +51,10 @@ clean:
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clean-all:clean
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make -C ../../../library/axi_ad6676 clean
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make -C ../../../library/xilinx/axi_adxcvr clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_jesd_gt clean
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make -C ../../../library/xilinx/util_adxcvr clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_jesd_gt clean
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ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS)
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@ -64,10 +64,10 @@ ad6676evb_vc707.sdk/system_top.hdf: $(M_DEPS)
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lib:
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make -C ../../../library/axi_ad6676
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make -C ../../../library/xilinx/axi_adxcvr
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_jesd_gt
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make -C ../../../library/xilinx/util_adxcvr
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make -C ../../../library/util_cpack
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make -C ../../../library/util_jesd_gt
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####################################################################################
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####################################################################################
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@ -31,4 +31,7 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4]
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# clocks
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create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
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create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
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set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
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@ -12,8 +12,6 @@ adi_project_files ad6676evb_vc707 [list \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/vc707/vc707_system_constr.xdc" ]
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set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
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adi_project_run ad6676evb_vc707
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@ -289,11 +289,13 @@ module system_top (
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.mgt_clk_clk_p (mgt_clk_p),
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.phy_rstn (phy_rstn),
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.phy_sd (1'b1),
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.rx_data_n (rx_data_n),
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.rx_data_p (rx_data_p),
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.rx_ref_clk (rx_ref_clk),
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.rx_sync (rx_sync),
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.rx_sysref (rx_sysref),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_ref_clk_0 (rx_ref_clk),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (rx_sysref),
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.sgmii_rxn (sgmii_rxn),
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.sgmii_rxp (sgmii_rxp),
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.sgmii_txn (sgmii_txn),
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@ -17,13 +17,13 @@ M_DEPS += ../../common/zc706/zc706_system_constr.xdc
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M_DEPS += ../../common/zc706/zc706_system_bd.tcl
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M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../../library/axi_ad6676/axi_ad6676.xpr
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M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
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M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr
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M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/xilinx/util_adxcvr/util_adxcvr.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_jesd_gt/util_jesd_gt.xpr
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M_VIVADO := vivado -mode batch -source
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@ -53,13 +53,13 @@ clean:
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clean-all:clean
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make -C ../../../library/axi_ad6676 clean
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make -C ../../../library/xilinx/axi_adxcvr clean
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make -C ../../../library/axi_clkgen clean
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make -C ../../../library/axi_dmac clean
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make -C ../../../library/axi_hdmi_tx clean
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make -C ../../../library/axi_jesd_gt clean
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make -C ../../../library/axi_spdif_tx clean
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make -C ../../../library/xilinx/util_adxcvr clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_jesd_gt clean
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ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS)
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@ -69,13 +69,13 @@ ad6676evb_zc706.sdk/system_top.hdf: $(M_DEPS)
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lib:
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make -C ../../../library/axi_ad6676
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make -C ../../../library/xilinx/axi_adxcvr
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make -C ../../../library/axi_clkgen
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make -C ../../../library/axi_dmac
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make -C ../../../library/axi_hdmi_tx
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make -C ../../../library/axi_jesd_gt
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make -C ../../../library/axi_spdif_tx
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make -C ../../../library/xilinx/util_adxcvr
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make -C ../../../library/util_cpack
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make -C ../../../library/util_jesd_gt
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####################################################################################
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####################################################################################
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@ -31,4 +31,7 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4
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# clocks
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create_clock -name rx_ref_clk -period 3.30 [get_ports rx_ref_clk_p]
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create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/axi_ad6676_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name rx_div_clk -period 6.60 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
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set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
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||||
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@ -12,8 +12,6 @@ adi_project_files ad6676evb_zc706 [list \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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||||
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
|
||||
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||||
set_property is_enabled false [get_files *axi_jesd_gt_tx_constr.xdc]
|
||||
|
||||
adi_project_run ad6676evb_zc706
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||||
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||||
|
||||
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|
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|||
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|
@ -270,11 +270,13 @@ module system_top (
|
|||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.ps_intr_12 (1'b0),
|
||||
.rx_data_n (rx_data_n),
|
||||
.rx_data_p (rx_data_p),
|
||||
.rx_ref_clk (rx_ref_clk),
|
||||
.rx_sync (rx_sync),
|
||||
.rx_sysref (rx_sysref),
|
||||
.rx_data_0_n (rx_data_n[0]),
|
||||
.rx_data_0_p (rx_data_p[0]),
|
||||
.rx_data_1_n (rx_data_n[1]),
|
||||
.rx_data_1_p (rx_data_p[1]),
|
||||
.rx_ref_clk_0 (rx_ref_clk),
|
||||
.rx_sync_0 (rx_sync),
|
||||
.rx_sysref_0 (rx_sysref),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (spi0_clk),
|
||||
.spi0_clk_o (spi0_clk),
|
||||
|
|
|
|||
Loading…
Reference in New Issue