Add missing timescale annotations
For consistent simulation behavior it is recommended to annotate all source files with a timescale. Add it to those where it is currently missing. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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251ea9471c
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d72fac4b1e
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@ -33,6 +33,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module avl_adxcvr_octet_swap #(
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module avl_adxcvr_octet_swap #(
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parameter NUM_OF_LANES = 1
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parameter NUM_OF_LANES = 1
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) (
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) (
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@ -33,6 +33,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_glue #(
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module jesd204_glue #(
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parameter WIDTH = 20,
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parameter WIDTH = 20,
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parameter CONST_WIDTH = 1,
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parameter CONST_WIDTH = 1,
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@ -34,6 +34,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// software programmable clock generator (still needs a reference input!)
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// software programmable clock generator (still needs a reference input!)
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`timescale 1ns/100ps
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module axi_clkgen #(
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module axi_clkgen #(
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parameter ID = 0,
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parameter ID = 0,
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@ -33,6 +33,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_2d_transfer #(
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module dmac_2d_transfer #(
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parameter DMA_AXI_ADDR_WIDTH = 32,
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parameter DMA_AXI_ADDR_WIDTH = 32,
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@ -33,6 +33,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_address_generator #(
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module dmac_address_generator #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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@ -33,6 +33,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac #(
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module axi_dmac #(
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parameter ID = 0,
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parameter ID = 0,
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@ -33,6 +33,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_burst_memory #(
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module axi_dmac_burst_memory #(
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parameter DATA_WIDTH_SRC = 64,
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parameter DATA_WIDTH_SRC = 64,
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parameter DATA_WIDTH_DEST = 64,
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parameter DATA_WIDTH_DEST = 64,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_regmap #(
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module axi_dmac_regmap #(
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parameter ID = 0,
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parameter ID = 0,
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parameter DISABLE_DEBUG_REGISTERS = 0,
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parameter DISABLE_DEBUG_REGISTERS = 0,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_regmap_request #(
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module axi_dmac_regmap_request #(
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parameter DISABLE_DEBUG_REGISTERS = 0,
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parameter DISABLE_DEBUG_REGISTERS = 0,
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parameter BYTES_PER_BEAT_WIDTH_DEST = 1,
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parameter BYTES_PER_BEAT_WIDTH_DEST = 1,
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@ -33,6 +33,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_reset_manager #(
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module axi_dmac_reset_manager #(
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parameter ASYNC_CLK_REQ_SRC = 1,
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parameter ASYNC_CLK_REQ_SRC = 1,
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parameter ASYNC_CLK_SRC_DEST = 1,
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parameter ASYNC_CLK_SRC_DEST = 1,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_resize_dest #(
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module axi_dmac_resize_dest #(
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parameter DATA_WIDTH_DEST = 64,
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parameter DATA_WIDTH_DEST = 64,
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parameter DATA_WIDTH_MEM = 64
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parameter DATA_WIDTH_MEM = 64
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@ -38,6 +38,8 @@
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* if necessary.
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* if necessary.
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*/
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*/
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`timescale 1ns/100ps
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module axi_dmac_resize_src #(
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module axi_dmac_resize_src #(
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parameter DATA_WIDTH_SRC = 64,
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parameter DATA_WIDTH_SRC = 64,
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parameter DATA_WIDTH_MEM = 64
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parameter DATA_WIDTH_MEM = 64
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_response_manager #(
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module axi_dmac_response_manager #(
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_transfer #(
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module axi_dmac_transfer #(
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_register_slice #(
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module axi_register_slice #(
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parameter DATA_WIDTH = 32,
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parameter DATA_WIDTH = 32,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_data_mover #(
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module dmac_data_mover #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_dest_mm_axi #(
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module dmac_dest_mm_axi #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_dest_axi_stream #(
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module dmac_dest_axi_stream #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_dest_fifo_inf #(
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module dmac_dest_fifo_inf #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_request_arb #(
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module dmac_request_arb #(
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_SRC = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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parameter DMA_DATA_WIDTH_DEST = 64,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_request_generator #(
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module dmac_request_generator #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_response_generator #(
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module dmac_response_generator #(
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parameter ID_WIDTH = 3)(
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parameter ID_WIDTH = 3)(
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_response_handler #(
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module dmac_response_handler #(
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parameter ID_WIDTH = 3)(
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parameter ID_WIDTH = 3)(
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module splitter #(
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module splitter #(
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_src_mm_axi #(
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module dmac_src_mm_axi #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_src_axi_stream #(
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module dmac_src_axi_stream #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_src_fifo_inf #(
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module dmac_src_fifo_inf #(
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parameter ID_WIDTH = 3,
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parameter ID_WIDTH = 3,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_read_slave #(
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module axi_read_slave #(
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parameter DATA_WIDTH = 32,
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parameter DATA_WIDTH = 32,
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parameter READ_ACCEPTANCE = 4,
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parameter READ_ACCEPTANCE = 4,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_slave #(
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module axi_slave #(
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parameter ACCEPTANCE = 3,
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parameter ACCEPTANCE = 3,
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parameter MIN_LATENCY = 16,
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parameter MIN_LATENCY = 16,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_write_slave #(
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module axi_write_slave #(
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parameter DATA_WIDTH = 32,
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parameter DATA_WIDTH = 32,
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parameter WRITE_ACCEPTANCE = 3
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parameter WRITE_ACCEPTANCE = 3
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_reset_manager_tb;
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module dmac_reset_manager_tb;
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parameter VCD_FILE = {`__FILE__,"cd"};
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parameter VCD_FILE = {`__FILE__,"cd"};
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_generic_adc (
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module axi_generic_adc (
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input adc_clk,
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input adc_clk,
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output [NUM_OF_CHANNELS-1:0] adc_enable,
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output [NUM_OF_CHANNELS-1:0] adc_enable,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_hdmi_rx #(
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module axi_hdmi_rx #(
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parameter ID = 0,
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parameter ID = 0,
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// ***************************************************************************
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// ***************************************************************************
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// Receive HDMI, hdmi embedded syncs data in, video dma data out.
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// Receive HDMI, hdmi embedded syncs data in, video dma data out.
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`timescale 1ns/100ps
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module axi_hdmi_rx_core #(
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module axi_hdmi_rx_core #(
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parameter IO_INTERFACE = 1) (
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parameter IO_INTERFACE = 1) (
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// ***************************************************************************
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// ***************************************************************************
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// Receive HDMI, hdmi embedded syncs data in, video dma data out.
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// Receive HDMI, hdmi embedded syncs data in, video dma data out.
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`timescale 1ns/100ps
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module axi_hdmi_rx_es #(
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module axi_hdmi_rx_es #(
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parameter DATA_WIDTH = 32) (
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parameter DATA_WIDTH = 32) (
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_hdmi_rx_tpm (
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module axi_hdmi_rx_tpm (
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input hdmi_clk,
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input hdmi_clk,
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input hdmi_sof,
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input hdmi_sof,
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_hdmi_tx #(
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module axi_hdmi_tx #(
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parameter ID = 0,
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parameter ID = 0,
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, video dma data in, hdmi separate syncs data out.
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// Transmit HDMI, video dma data in, hdmi separate syncs data out.
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`timescale 1ns/100ps
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module axi_hdmi_tx_core #(
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module axi_hdmi_tx_core #(
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parameter CR_CB_N = 0,
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parameter CR_CB_N = 0,
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, video dma data in, hdmi separate syncs data out.
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// Transmit HDMI, video dma data in, hdmi separate syncs data out.
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`timescale 1ns/100ps
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module axi_hdmi_tx_es #(
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module axi_hdmi_tx_es #(
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parameter DATA_WIDTH = 32) (
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parameter DATA_WIDTH = 32) (
|
||||||
|
|
|
@ -34,6 +34,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
|
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module axi_hdmi_tx_vdma (
|
module axi_hdmi_tx_vdma (
|
||||||
|
|
||||||
// hdmi interface
|
// hdmi interface
|
||||||
|
|
|
@ -33,6 +33,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module control_registers
|
module control_registers
|
||||||
(
|
(
|
||||||
|
|
||||||
|
|
|
@ -38,6 +38,8 @@
|
||||||
* single read-write AXI interface. Only supports AXI3 at the moment.
|
* single read-write AXI interface. Only supports AXI3 at the moment.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module axi_rd_wr_combiner (
|
module axi_rd_wr_combiner (
|
||||||
input clk,
|
input clk,
|
||||||
|
|
||||||
|
|
|
@ -33,6 +33,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module cn0363_dma_sequencer (
|
module cn0363_dma_sequencer (
|
||||||
input clk,
|
input clk,
|
||||||
input resetn,
|
input resetn,
|
||||||
|
|
|
@ -33,6 +33,7 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module cn0363_phase_data_sync (
|
module cn0363_phase_data_sync (
|
||||||
input clk,
|
input clk,
|
||||||
|
|
|
@ -34,6 +34,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
|
// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module ad_csc_1 #(
|
module ad_csc_1 #(
|
||||||
|
|
||||||
parameter DELAY_DATA_WIDTH = 16) (
|
parameter DELAY_DATA_WIDTH = 16) (
|
||||||
|
|
|
@ -39,6 +39,8 @@
|
||||||
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
|
// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
|
||||||
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
|
// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module ad_csc_CrYCb2RGB #(
|
module ad_csc_CrYCb2RGB #(
|
||||||
|
|
||||||
parameter DELAY_DATA_WIDTH = 16) (
|
parameter DELAY_DATA_WIDTH = 16) (
|
||||||
|
|
|
@ -39,6 +39,8 @@
|
||||||
// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
|
// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
|
||||||
// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
|
// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module ad_csc_RGB2CrYCb #(
|
module ad_csc_RGB2CrYCb #(
|
||||||
|
|
||||||
parameter DELAY_DATA_WIDTH = 16) (
|
parameter DELAY_DATA_WIDTH = 16) (
|
||||||
|
|
|
@ -34,6 +34,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Input must be RGB or CrYCb in that order, output is CrY/CbY
|
// Input must be RGB or CrYCb in that order, output is CrY/CbY
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module ad_ss_422to444 #(
|
module ad_ss_422to444 #(
|
||||||
|
|
||||||
parameter CR_CB_N = 0,
|
parameter CR_CB_N = 0,
|
||||||
|
|
|
@ -34,6 +34,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// Input must be RGB or CrYCb in that order, output is CrY/CbY
|
// Input must be RGB or CrYCb in that order, output is CrY/CbY
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module ad_ss_444to422 #(
|
module ad_ss_444to422 #(
|
||||||
|
|
||||||
parameter CR_CB_N = 0,
|
parameter CR_CB_N = 0,
|
||||||
|
|
|
@ -33,6 +33,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module up_hdmi_rx #(
|
module up_hdmi_rx #(
|
||||||
|
|
||||||
parameter ID = 0) (
|
parameter ID = 0) (
|
||||||
|
|
|
@ -38,6 +38,8 @@
|
||||||
// the data format inside a generic AXI converter core.
|
// the data format inside a generic AXI converter core.
|
||||||
// + Supports multiple channels. Contains a single register stage.
|
// + Supports multiple channels. Contains a single register stage.
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module util_axis_upscale # (
|
module util_axis_upscale # (
|
||||||
|
|
||||||
parameter NUM_OF_CHANNELS = 4,
|
parameter NUM_OF_CHANNELS = 4,
|
||||||
|
|
|
@ -33,6 +33,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module cordic_demod (
|
module cordic_demod (
|
||||||
input clk,
|
input clk,
|
||||||
input resetn,
|
input resetn,
|
||||||
|
|
|
@ -21,7 +21,7 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module ad_ip_jesd204_tpl_adc_regmap #(
|
module ad_ip_jesd204_tpl_adc_regmap #(
|
||||||
parameter ID = 0,
|
parameter ID = 0,
|
||||||
|
|
|
@ -21,6 +21,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module ad_ip_jesd204_tpl_dac_regmap #(
|
module ad_ip_jesd204_tpl_dac_regmap #(
|
||||||
parameter ID = 0,
|
parameter ID = 0,
|
||||||
parameter NUM_CHANNELS = 2,
|
parameter NUM_CHANNELS = 2,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_up_common # (
|
module jesd204_up_common # (
|
||||||
parameter PCORE_VERSION = 0,
|
parameter PCORE_VERSION = 0,
|
||||||
parameter PCORE_MAGIC = 0,
|
parameter PCORE_MAGIC = 0,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_up_sysref (
|
module jesd204_up_sysref (
|
||||||
input up_clk,
|
input up_clk,
|
||||||
input up_reset,
|
input up_reset,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module axi_jesd204_rx #(
|
module axi_jesd204_rx #(
|
||||||
parameter ID = 0,
|
parameter ID = 0,
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_up_ilas_mem (
|
module jesd204_up_ilas_mem (
|
||||||
input up_clk,
|
input up_clk,
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_up_rx # (
|
module jesd204_up_rx # (
|
||||||
parameter NUM_LANES = 1
|
parameter NUM_LANES = 1
|
||||||
) (
|
) (
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_up_rx_lane (
|
module jesd204_up_rx_lane (
|
||||||
input up_clk,
|
input up_clk,
|
||||||
input up_reset_synchronizer,
|
input up_reset_synchronizer,
|
||||||
|
|
|
@ -42,6 +42,7 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module axi_jesd204_tx #(
|
module axi_jesd204_tx #(
|
||||||
parameter ID = 0,
|
parameter ID = 0,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_up_tx # (
|
module jesd204_up_tx # (
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter NUM_LINKS = 1
|
parameter NUM_LINKS = 1
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_eof_generator #(
|
module jesd204_eof_generator #(
|
||||||
parameter DATA_PATH_WIDTH = 4,
|
parameter DATA_PATH_WIDTH = 4,
|
||||||
parameter MAX_OCTETS_PER_FRAME = 256
|
parameter MAX_OCTETS_PER_FRAME = 256
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_lmfc (
|
module jesd204_lmfc (
|
||||||
input clk,
|
input clk,
|
||||||
input reset,
|
input reset,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_scrambler #(
|
module jesd204_scrambler #(
|
||||||
parameter WIDTH = 32,
|
parameter WIDTH = 32,
|
||||||
parameter DESCRAMBLE = 0
|
parameter DESCRAMBLE = 0
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module pipeline_stage #(
|
module pipeline_stage #(
|
||||||
parameter REGISTERED = 1,
|
parameter REGISTERED = 1,
|
||||||
parameter WIDTH = 1
|
parameter WIDTH = 1
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module align_mux #(
|
module align_mux #(
|
||||||
parameter DATA_PATH_WIDTH = 4
|
parameter DATA_PATH_WIDTH = 4
|
||||||
) (
|
) (
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module elastic_buffer #(
|
module elastic_buffer #(
|
||||||
parameter WIDTH = 32,
|
parameter WIDTH = 32,
|
||||||
parameter SIZE = 256
|
parameter SIZE = 256
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_ilas_monitor #(
|
module jesd204_ilas_monitor #(
|
||||||
parameter DATA_PATH_WIDTH = 4
|
parameter DATA_PATH_WIDTH = 4
|
||||||
) (
|
) (
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_lane_latency_monitor #(
|
module jesd204_lane_latency_monitor #(
|
||||||
parameter NUM_LANES = 1
|
parameter NUM_LANES = 1
|
||||||
) (
|
) (
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_rx #(
|
module jesd204_rx #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter NUM_LINKS = 1
|
parameter NUM_LINKS = 1
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_rx_cgs #(
|
module jesd204_rx_cgs #(
|
||||||
parameter DATA_PATH_WIDTH = 4
|
parameter DATA_PATH_WIDTH = 4
|
||||||
) (
|
) (
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_rx_ctrl #(
|
module jesd204_rx_ctrl #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter NUM_LINKS = 1
|
parameter NUM_LINKS = 1
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_rx_lane #(
|
module jesd204_rx_lane #(
|
||||||
parameter DATA_PATH_WIDTH = 4,
|
parameter DATA_PATH_WIDTH = 4,
|
||||||
parameter CHAR_INFO_REGISTERED = 0,
|
parameter CHAR_INFO_REGISTERED = 0,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_rx_static_config #(
|
module jesd204_rx_static_config #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter NUM_LINKS = 1,
|
parameter NUM_LINKS = 1,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_8b10b_decoder (
|
module jesd204_8b10b_decoder (
|
||||||
input in_disparity,
|
input in_disparity,
|
||||||
input [9:0] in_char,
|
input [9:0] in_char,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_pattern_align #(
|
module jesd204_pattern_align #(
|
||||||
parameter DATA_PATH_WIDTH = 4
|
parameter DATA_PATH_WIDTH = 4
|
||||||
) (
|
) (
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_soft_pcs_rx #(
|
module jesd204_soft_pcs_rx #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter DATA_PATH_WIDTH = 4,
|
parameter DATA_PATH_WIDTH = 4,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_8b10b_encoder (
|
module jesd204_8b10b_encoder (
|
||||||
input in_disparity,
|
input in_disparity,
|
||||||
input [7:0] in_char,
|
input [7:0] in_char,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_soft_pcs_tx #(
|
module jesd204_soft_pcs_tx #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter DATA_PATH_WIDTH = 4,
|
parameter DATA_PATH_WIDTH = 4,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_tx #(
|
module jesd204_tx #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter NUM_LINKS = 1
|
parameter NUM_LINKS = 1
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_tx_ctrl #(
|
module jesd204_tx_ctrl #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter NUM_LINKS = 1,
|
parameter NUM_LINKS = 1,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_tx_lane #(
|
module jesd204_tx_lane #(
|
||||||
parameter DATA_PATH_WIDTH = 4
|
parameter DATA_PATH_WIDTH = 4
|
||||||
) (
|
) (
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_ilas_config_static #(
|
module jesd204_ilas_config_static #(
|
||||||
parameter DID = 8'h00,
|
parameter DID = 8'h00,
|
||||||
parameter BID = 4'h0,
|
parameter BID = 4'h0,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module jesd204_tx_static_config #(
|
module jesd204_tx_static_config #(
|
||||||
parameter NUM_LANES = 1,
|
parameter NUM_LANES = 1,
|
||||||
parameter NUM_LINKS = 1,
|
parameter NUM_LINKS = 1,
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module axi_jesd204_rx_tb;
|
module axi_jesd204_rx_tb;
|
||||||
parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd";
|
parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd";
|
||||||
parameter NUM_LANES = 2;
|
parameter NUM_LANES = 2;
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module axi_jesd204_tx_tb;
|
module axi_jesd204_tx_tb;
|
||||||
parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd";
|
parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd";
|
||||||
parameter NUM_LANES = 2;
|
parameter NUM_LANES = 2;
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module loopback_tb;
|
module loopback_tb;
|
||||||
parameter VCD_FILE = "loopback_tb.vcd";
|
parameter VCD_FILE = "loopback_tb.vcd";
|
||||||
parameter NUM_LANES = 4;
|
parameter NUM_LANES = 4;
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module rx_cgs_tb;
|
module rx_cgs_tb;
|
||||||
parameter VCD_FILE = "rx_cgs_tb.vcd";
|
parameter VCD_FILE = "rx_cgs_tb.vcd";
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module rx_ctrl_tb;
|
module rx_ctrl_tb;
|
||||||
parameter VCD_FILE = "rx_ctrl_tb.vcd";
|
parameter VCD_FILE = "rx_ctrl_tb.vcd";
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module rx_lane_tb;
|
module rx_lane_tb;
|
||||||
parameter VCD_FILE = "rx_lane_tb.vcd";
|
parameter VCD_FILE = "rx_lane_tb.vcd";
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module rx_tb;
|
module rx_tb;
|
||||||
parameter VCD_FILE = "rx_tb.vcd";
|
parameter VCD_FILE = "rx_tb.vcd";
|
||||||
parameter NUM_LANES = 1;
|
parameter NUM_LANES = 1;
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module scrambler_tb;
|
module scrambler_tb;
|
||||||
parameter VCD_FILE = "scrambler_tb.vcd";
|
parameter VCD_FILE = "scrambler_tb.vcd";
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module soft_pcs_8b10b_sequence_tb;
|
module soft_pcs_8b10b_sequence_tb;
|
||||||
parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
|
parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module soft_pcs_8b10b_table_tb;
|
module soft_pcs_8b10b_table_tb;
|
||||||
parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd";
|
parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd";
|
||||||
|
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module soft_pcs_loopback_tb;
|
module soft_pcs_loopback_tb;
|
||||||
parameter VCD_FILE = "soft_pcs_loopback_tb.vcd";
|
parameter VCD_FILE = "soft_pcs_loopback_tb.vcd";
|
||||||
parameter DATA_PATH_WIDTH = 4;
|
parameter DATA_PATH_WIDTH = 4;
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module soft_pcs_pattern_align_tb;
|
module soft_pcs_pattern_align_tb;
|
||||||
parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
|
parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
|
||||||
|
|
||||||
|
|
|
@ -48,6 +48,8 @@
|
||||||
* cycle.
|
* cycle.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module tx_ctrl_phase_tb;
|
module tx_ctrl_phase_tb;
|
||||||
parameter VCD_FILE = "tx_ctrl_phase.vcd";
|
parameter VCD_FILE = "tx_ctrl_phase.vcd";
|
||||||
parameter NUM_LANES = 1;
|
parameter NUM_LANES = 1;
|
||||||
|
|
|
@ -42,6 +42,8 @@
|
||||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||||
//
|
//
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module tx_tb;
|
module tx_tb;
|
||||||
parameter VCD_FILE = "tx_tb.vcd";
|
parameter VCD_FILE = "tx_tb.vcd";
|
||||||
parameter NUM_LANES = 4;
|
parameter NUM_LANES = 4;
|
||||||
|
@ -57,6 +59,7 @@ module tx_tb;
|
||||||
reg [31:0] tx_data = 'h00000000;
|
reg [31:0] tx_data = 'h00000000;
|
||||||
|
|
||||||
wire tx_ready;
|
wire tx_ready;
|
||||||
|
wire tx_valid = 1'b1;
|
||||||
wire [NUM_LANES-1:0] cfg_lanes_disable;
|
wire [NUM_LANES-1:0] cfg_lanes_disable;
|
||||||
wire [NUM_LINKS-1:0] cfg_links_disable;
|
wire [NUM_LINKS-1:0] cfg_links_disable;
|
||||||
wire [7:0] cfg_beats_per_multiframe;
|
wire [7:0] cfg_beats_per_multiframe;
|
||||||
|
@ -112,6 +115,8 @@ module tx_tb;
|
||||||
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
.OCTETS_PER_FRAME(OCTETS_PER_FRAME),
|
||||||
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
|
.FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
|
||||||
) i_cfg (
|
) i_cfg (
|
||||||
|
.clk(clk),
|
||||||
|
|
||||||
.cfg_lanes_disable(cfg_lanes_disable),
|
.cfg_lanes_disable(cfg_lanes_disable),
|
||||||
.cfg_links_disable(cfg_links_disable),
|
.cfg_links_disable(cfg_links_disable),
|
||||||
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
|
||||||
|
@ -159,6 +164,7 @@ module tx_tb;
|
||||||
.ctrl_manual_sync_request (1'b0),
|
.ctrl_manual_sync_request (1'b0),
|
||||||
|
|
||||||
.tx_ready(tx_ready),
|
.tx_ready(tx_ready),
|
||||||
|
.tx_valid(tx_valid),
|
||||||
.tx_data({NUM_LANES{tx_data}}),
|
.tx_data({NUM_LANES{tx_data}}),
|
||||||
|
|
||||||
.sync(sync),
|
.sync(sync),
|
||||||
|
|
|
@ -33,6 +33,8 @@
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
// ***************************************************************************
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
module spi_engine_execution #(
|
module spi_engine_execution #(
|
||||||
|
|
||||||
parameter NUM_OF_CS = 1,
|
parameter NUM_OF_CS = 1,
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue