Add missing timescale annotations

For consistent simulation behavior it is recommended to annotate all source
files with a timescale. Add it to those where it is currently missing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/altera/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module avl_adxcvr_octet_swap #(
   parameter NUM_OF_LANES = 1
 ) (

library/altera/jesd204_phy/jesd204_phy_glue.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module jesd204_glue #(
   parameter WIDTH = 20,
   parameter CONST_WIDTH = 1,

library/axi_clkgen/axi_clkgen.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // software programmable clock generator (still needs a reference input!)
 
+`timescale 1ns/100ps
+
 module axi_clkgen #(
 
   parameter         ID = 0,

library/axi_dmac/2d_transfer.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_2d_transfer #(
 
   parameter DMA_AXI_ADDR_WIDTH = 32,

library/axi_dmac/address_generator.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_address_generator #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/axi_dmac.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac #(
 
   parameter ID = 0,

library/axi_dmac/axi_dmac_burst_memory.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac_burst_memory #(
   parameter DATA_WIDTH_SRC = 64,
   parameter DATA_WIDTH_DEST = 64,

library/axi_dmac/axi_dmac_regmap.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac_regmap #(
   parameter ID = 0,
   parameter DISABLE_DEBUG_REGISTERS = 0,

library/axi_dmac/axi_dmac_regmap_request.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac_regmap_request #(
   parameter DISABLE_DEBUG_REGISTERS = 0,
   parameter BYTES_PER_BEAT_WIDTH_DEST = 1,

library/axi_dmac/axi_dmac_reset_manager.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac_reset_manager #(
   parameter ASYNC_CLK_REQ_SRC = 1,
   parameter ASYNC_CLK_SRC_DEST = 1,

library/axi_dmac/axi_dmac_resize_dest.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac_resize_dest #(
   parameter DATA_WIDTH_DEST = 64,
   parameter DATA_WIDTH_MEM = 64

library/axi_dmac/axi_dmac_resize_src.v

@@ -38,6 +38,8 @@
  * if necessary.
  */
 
+`timescale 1ns/100ps
+
 module axi_dmac_resize_src #(
   parameter DATA_WIDTH_SRC = 64,
   parameter DATA_WIDTH_MEM = 64

library/axi_dmac/axi_dmac_response_manager.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac_response_manager #(
   parameter DMA_DATA_WIDTH_SRC = 64,
   parameter DMA_DATA_WIDTH_DEST = 64,

library/axi_dmac/axi_dmac_transfer.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_dmac_transfer #(
   parameter DMA_DATA_WIDTH_SRC = 64,
   parameter DMA_DATA_WIDTH_DEST = 64,

library/axi_dmac/axi_register_slice.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_register_slice #(
 
   parameter DATA_WIDTH = 32,

library/axi_dmac/data_mover.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_data_mover #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/dest_axi_mm.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_dest_mm_axi #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/dest_axi_stream.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_dest_axi_stream #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/dest_fifo_inf.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_dest_fifo_inf #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/request_arb.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_request_arb #(
   parameter DMA_DATA_WIDTH_SRC = 64,
   parameter DMA_DATA_WIDTH_DEST = 64,

library/axi_dmac/request_generator.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_request_generator #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/response_generator.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_response_generator #(
 
   parameter ID_WIDTH = 3)(

library/axi_dmac/response_handler.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_response_handler #(
 
   parameter ID_WIDTH = 3)(

library/axi_dmac/splitter.v

@@ -33,6 +33,7 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
 
 module splitter #(
 

library/axi_dmac/src_axi_mm.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_src_mm_axi #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/src_axi_stream.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_src_axi_stream #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/src_fifo_inf.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_src_fifo_inf #(
 
   parameter ID_WIDTH = 3,

library/axi_dmac/tb/axi_read_slave.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_read_slave #(
   parameter DATA_WIDTH = 32,
   parameter READ_ACCEPTANCE = 4,

library/axi_dmac/tb/axi_slave.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_slave #(
   parameter ACCEPTANCE = 3,
   parameter MIN_LATENCY = 16,

library/axi_dmac/tb/axi_write_slave.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_write_slave #(
   parameter DATA_WIDTH = 32,
   parameter WRITE_ACCEPTANCE = 3

library/axi_dmac/tb/reset_manager_tb.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module dmac_reset_manager_tb;
   parameter VCD_FILE = {`__FILE__,"cd"};
 

library/axi_generic_adc/axi_generic_adc.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_generic_adc (
   input adc_clk,
   output [NUM_OF_CHANNELS-1:0] adc_enable,

library/axi_hdmi_rx/axi_hdmi_rx.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_hdmi_rx  #(
 
   parameter   ID = 0,

library/axi_hdmi_rx/axi_hdmi_rx_core.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // Receive HDMI, hdmi embedded syncs data in, video dma data out.
 
+`timescale 1ns/100ps
+
 module axi_hdmi_rx_core #(
   
   parameter   IO_INTERFACE = 1) (

library/axi_hdmi_rx/axi_hdmi_rx_es.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // Receive HDMI, hdmi embedded syncs data in, video dma data out.
 
+`timescale 1ns/100ps
+
 module axi_hdmi_rx_es #(
 
   parameter   DATA_WIDTH = 32) (

library/axi_hdmi_rx/axi_hdmi_rx_tpm.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_hdmi_rx_tpm (
   input                   hdmi_clk,
   input                   hdmi_sof,

library/axi_hdmi_tx/axi_hdmi_tx.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module axi_hdmi_tx #(
 
   parameter   ID = 0,

library/axi_hdmi_tx/axi_hdmi_tx_core.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // Transmit HDMI, video dma data in, hdmi separate syncs data out.
 
+`timescale 1ns/100ps
+
 module axi_hdmi_tx_core #(
 
   parameter   CR_CB_N = 0,

library/axi_hdmi_tx/axi_hdmi_tx_es.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // Transmit HDMI, video dma data in, hdmi separate syncs data out.
 
+`timescale 1ns/100ps
+
 module axi_hdmi_tx_es #(
 
   parameter   DATA_WIDTH = 32) (

library/axi_hdmi_tx/axi_hdmi_tx_vdma.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // Transmit HDMI, video dma data in, hdmi separate syncs data out.
 
+`timescale 1ns/100ps
+
 module axi_hdmi_tx_vdma (
 
   // hdmi interface

library/axi_mc_controller/control_registers.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module control_registers
 (
 

library/axi_rd_wr_combiner/axi_rd_wr_combiner.v

@@ -38,6 +38,8 @@
  * single read-write AXI interface. Only supports AXI3 at the moment.
  */
 
+`timescale 1ns/100ps
+
 module axi_rd_wr_combiner (
   input                         clk,
 

library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module cn0363_dma_sequencer (
   input clk,
   input resetn,

library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v

@@ -33,6 +33,7 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
 
 module cn0363_phase_data_sync (
   input clk,

library/common/ad_csc_1.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
 
+`timescale 1ns/100ps
+
 module ad_csc_1 #(
 
   parameter   DELAY_DATA_WIDTH = 16) (

library/common/ad_csc_CrYCb2RGB.v

@@ -39,6 +39,8 @@
 // G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576);
 // B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836);
 
+`timescale 1ns/100ps
+
 module ad_csc_CrYCb2RGB #(
 
   parameter   DELAY_DATA_WIDTH = 16) (

library/common/ad_csc_RGB2CrYCb.v

@@ -39,6 +39,8 @@
 // Y  = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B +  16;
 // Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
 
+`timescale 1ns/100ps
+
 module ad_csc_RGB2CrYCb #(
 
   parameter   DELAY_DATA_WIDTH = 16) (

library/common/ad_ss_422to444.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // Input must be RGB or CrYCb in that order, output is CrY/CbY
 
+`timescale 1ns/100ps
+
 module ad_ss_422to444 #(
 
   parameter   CR_CB_N = 0,

library/common/ad_ss_444to422.v

@@ -34,6 +34,8 @@
 // ***************************************************************************
 // Input must be RGB or CrYCb in that order, output is CrY/CbY
 
+`timescale 1ns/100ps
+
 module ad_ss_444to422 #(
 
   parameter   CR_CB_N = 0,

library/common/up_hdmi_rx.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module up_hdmi_rx #(
 
   parameter   ID = 0) (

library/common/util_axis_upscale.v

@@ -38,6 +38,8 @@
 //    the data format inside a generic AXI converter core.
 //  + Supports multiple channels. Contains a single register stage.
 
+`timescale 1ns/100ps
+
 module util_axis_upscale # (
 
   parameter NUM_OF_CHANNELS = 4,

library/cordic_demod/cordic_demod.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module cordic_demod (
   input clk,
   input resetn,

library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v

@@ -21,7 +21,7 @@
 // ***************************************************************************
 // ***************************************************************************
 
-
+`timescale 1ns/100ps
 
 module ad_ip_jesd204_tpl_adc_regmap #(
   parameter ID = 0,

library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v

@@ -21,6 +21,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module ad_ip_jesd204_tpl_dac_regmap #(
   parameter ID = 0,
   parameter NUM_CHANNELS = 2,

library/jesd204/axi_jesd204_common/jesd204_up_common.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_up_common # (
   parameter PCORE_VERSION = 0,
   parameter PCORE_MAGIC = 0,

library/jesd204/axi_jesd204_common/jesd204_up_sysref.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_up_sysref (
   input up_clk,
   input up_reset,

library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module axi_jesd204_rx #(
   parameter ID = 0,
   parameter NUM_LANES = 1,

library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_up_ilas_mem (
   input up_clk,
 

library/jesd204/axi_jesd204_rx/jesd204_up_rx.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_up_rx # (
   parameter NUM_LANES = 1
 ) (

library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_up_rx_lane (
   input up_clk,
   input up_reset_synchronizer,

library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v

@@ -42,6 +42,7 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
 
 module axi_jesd204_tx #(
   parameter ID = 0,

library/jesd204/axi_jesd204_tx/jesd204_up_tx.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_up_tx # (
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1

library/jesd204/jesd204_common/jesd204_eof_generator.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_eof_generator #(
   parameter DATA_PATH_WIDTH = 4,
   parameter MAX_OCTETS_PER_FRAME = 256

library/jesd204/jesd204_common/jesd204_lmfc.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_lmfc (
   input clk,
   input reset,

library/jesd204/jesd204_common/jesd204_scrambler.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_scrambler #(
   parameter WIDTH = 32,
   parameter DESCRAMBLE = 0

library/jesd204/jesd204_common/pipeline_stage.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module pipeline_stage #(
   parameter REGISTERED = 1,
   parameter WIDTH = 1

library/jesd204/jesd204_rx/align_mux.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module align_mux #(
   parameter DATA_PATH_WIDTH = 4
 ) (

library/jesd204/jesd204_rx/elastic_buffer.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module elastic_buffer #(
   parameter WIDTH = 32,
   parameter SIZE = 256

library/jesd204/jesd204_rx/jesd204_ilas_monitor.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_ilas_monitor #(
   parameter DATA_PATH_WIDTH = 4
 ) (

library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_lane_latency_monitor #(
   parameter NUM_LANES = 1
 ) (

library/jesd204/jesd204_rx/jesd204_rx.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_rx #(
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1

library/jesd204/jesd204_rx/jesd204_rx_cgs.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_rx_cgs #(
   parameter DATA_PATH_WIDTH = 4
 ) (

library/jesd204/jesd204_rx/jesd204_rx_ctrl.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_rx_ctrl #(
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1

library/jesd204/jesd204_rx/jesd204_rx_lane.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_rx_lane #(
   parameter DATA_PATH_WIDTH = 4,
   parameter CHAR_INFO_REGISTERED = 0,

library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_rx_static_config #(
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1,

library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_8b10b_decoder (
   input in_disparity,
   input [9:0] in_char,

library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_pattern_align #(
   parameter DATA_PATH_WIDTH = 4
 ) (

library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_soft_pcs_rx #(
   parameter NUM_LANES = 1,
   parameter DATA_PATH_WIDTH = 4,

library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_8b10b_encoder (
   input in_disparity,
   input [7:0] in_char,

library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_soft_pcs_tx #(
   parameter NUM_LANES = 1,
   parameter DATA_PATH_WIDTH = 4,

library/jesd204/jesd204_tx/jesd204_tx.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_tx #(
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1

library/jesd204/jesd204_tx/jesd204_tx_ctrl.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_tx_ctrl #(
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1,

library/jesd204/jesd204_tx/jesd204_tx_lane.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_tx_lane #(
   parameter DATA_PATH_WIDTH = 4
 ) (

library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_ilas_config_static #(
   parameter DID = 8'h00,
   parameter BID = 4'h0,

library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module jesd204_tx_static_config #(
   parameter NUM_LANES = 1,
   parameter NUM_LINKS = 1,

library/jesd204/tb/axi_jesd204_rx_regmap_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module axi_jesd204_rx_tb;
   parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd";
   parameter NUM_LANES = 2;

library/jesd204/tb/axi_jesd204_tx_regmap_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module axi_jesd204_tx_tb;
   parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd";
   parameter NUM_LANES = 2;

library/jesd204/tb/loopback_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module loopback_tb;
   parameter VCD_FILE = "loopback_tb.vcd";
   parameter NUM_LANES = 4;

library/jesd204/tb/rx_cgs_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module rx_cgs_tb;
   parameter VCD_FILE = "rx_cgs_tb.vcd";
 

library/jesd204/tb/rx_ctrl_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module rx_ctrl_tb;
   parameter VCD_FILE = "rx_ctrl_tb.vcd";
 

library/jesd204/tb/rx_lane_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module rx_lane_tb;
   parameter VCD_FILE = "rx_lane_tb.vcd";
 

library/jesd204/tb/rx_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module rx_tb;
   parameter VCD_FILE = "rx_tb.vcd";
   parameter NUM_LANES = 1;

library/jesd204/tb/scrambler_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module scrambler_tb;
   parameter VCD_FILE = "scrambler_tb.vcd";
 

library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module soft_pcs_8b10b_sequence_tb;
   parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
 

library/jesd204/tb/soft_pcs_8b10b_table_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module soft_pcs_8b10b_table_tb;
   parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd";
 

library/jesd204/tb/soft_pcs_loopback_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module soft_pcs_loopback_tb;
   parameter VCD_FILE = "soft_pcs_loopback_tb.vcd";
   parameter DATA_PATH_WIDTH = 4;

library/jesd204/tb/soft_pcs_pattern_align_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module soft_pcs_pattern_align_tb;
   parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd";
 

library/jesd204/tb/tx_ctrl_phase_tb.v

@@ -48,6 +48,8 @@
  * cycle.
  */
 
+`timescale 1ns/100ps
+
 module tx_ctrl_phase_tb;
   parameter VCD_FILE = "tx_ctrl_phase.vcd";
   parameter NUM_LANES = 1;

library/jesd204/tb/tx_tb.v

@@ -42,6 +42,8 @@
 // is copyright © 2016-2017, Analog Devices, Inc.”
 //
 
+`timescale 1ns/100ps
+
 module tx_tb;
   parameter VCD_FILE = "tx_tb.vcd";
   parameter NUM_LANES = 4;
@@ -57,6 +59,7 @@ module tx_tb;
   reg [31:0] tx_data = 'h00000000;
 
   wire tx_ready;
+  wire tx_valid = 1'b1;
   wire [NUM_LANES-1:0] cfg_lanes_disable;
   wire [NUM_LINKS-1:0] cfg_links_disable;
   wire [7:0] cfg_beats_per_multiframe;
@@ -112,6 +115,8 @@ module tx_tb;
     .OCTETS_PER_FRAME(OCTETS_PER_FRAME),
     .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
   ) i_cfg (
+    .clk(clk),
+
     .cfg_lanes_disable(cfg_lanes_disable),
     .cfg_links_disable(cfg_links_disable),
     .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
@@ -159,6 +164,7 @@ module tx_tb;
     .ctrl_manual_sync_request (1'b0),
 
     .tx_ready(tx_ready),
+    .tx_valid(tx_valid),
     .tx_data({NUM_LANES{tx_data}}),
 
     .sync(sync),

library/spi_engine/spi_engine_execution/spi_engine_execution.v

@@ -33,6 +33,8 @@
 // ***************************************************************************
 // ***************************************************************************
 
+`timescale 1ns/100ps
+
 module spi_engine_execution #(
 
   parameter NUM_OF_CS = 1,