util_adxcvr: Add 204C support for GTH3/4
For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock that is 2x of the CLKUSR2 (lane rate/66), CLKUSR = 2 x CLKUSR2 CLKUSR = lane rate / 33 This can be driven from the GT reference clock or second out clock div2. This commit also: - fix eyescan scale on GTY - remove irrelevant parametersmain
Laszlo Nagy
Laszlo Nagy
parent
c0775adac3
commit
d743406ecd
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@ -134,7 +134,9 @@ module util_adxcvr #(
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input rx_0_p,
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input rx_0_p,
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input rx_0_n,
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input rx_0_n,
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output rx_out_clk_0,
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output rx_out_clk_0,
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output rx_out_clk_div2_0,
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input rx_clk_0,
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input rx_clk_0,
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input rx_clk_2x_0,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_0,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_0,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_0,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_0,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_0,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_0,
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@ -146,7 +148,9 @@ module util_adxcvr #(
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output tx_0_p,
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output tx_0_p,
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output tx_0_n,
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output tx_0_n,
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output tx_out_clk_0,
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output tx_out_clk_0,
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output tx_out_clk_div2_0,
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input tx_clk_0,
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input tx_clk_0,
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input tx_clk_2x_0,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_0,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_0,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_0,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_0,
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input [1:0] tx_header_0,
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input [1:0] tx_header_0,
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@ -208,7 +212,9 @@ module util_adxcvr #(
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input rx_1_p,
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input rx_1_p,
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input rx_1_n,
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input rx_1_n,
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output rx_out_clk_1,
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output rx_out_clk_1,
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output rx_out_clk_div2_1,
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input rx_clk_1,
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input rx_clk_1,
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input rx_clk_2x_1,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_1,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_1,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_1,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_1,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_1,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_1,
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@ -220,7 +226,9 @@ module util_adxcvr #(
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output tx_1_p,
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output tx_1_p,
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output tx_1_n,
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output tx_1_n,
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output tx_out_clk_1,
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output tx_out_clk_1,
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output tx_out_clk_div2_1,
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input tx_clk_1,
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input tx_clk_1,
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input tx_clk_2x_1,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_1,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_1,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_1,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_1,
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input [1:0] tx_header_1,
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input [1:0] tx_header_1,
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@ -276,7 +284,9 @@ module util_adxcvr #(
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input rx_2_p,
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input rx_2_p,
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input rx_2_n,
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input rx_2_n,
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output rx_out_clk_2,
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output rx_out_clk_2,
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output rx_out_clk_div2_2,
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input rx_clk_2,
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input rx_clk_2,
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input rx_clk_2x_2,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_2,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_2,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_2,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_2,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_2,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_2,
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@ -288,7 +298,9 @@ module util_adxcvr #(
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output tx_2_p,
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output tx_2_p,
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output tx_2_n,
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output tx_2_n,
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output tx_out_clk_2,
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output tx_out_clk_2,
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output tx_out_clk_div2_2,
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input tx_clk_2,
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input tx_clk_2,
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input tx_clk_2x_2,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_2,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_2,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_2,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_2,
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input [1:0] tx_header_2,
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input [1:0] tx_header_2,
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@ -344,7 +356,9 @@ module util_adxcvr #(
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input rx_3_p,
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input rx_3_p,
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input rx_3_n,
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input rx_3_n,
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output rx_out_clk_3,
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output rx_out_clk_3,
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output rx_out_clk_div2_3,
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input rx_clk_3,
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input rx_clk_3,
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input rx_clk_2x_3,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_3,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_3,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_3,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_3,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_3,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_3,
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@ -356,7 +370,9 @@ module util_adxcvr #(
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output tx_3_p,
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output tx_3_p,
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output tx_3_n,
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output tx_3_n,
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output tx_out_clk_3,
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output tx_out_clk_3,
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output tx_out_clk_div2_3,
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input tx_clk_3,
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input tx_clk_3,
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input tx_clk_2x_3,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_3,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_3,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_3,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_3,
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input [1:0] tx_header_3,
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input [1:0] tx_header_3,
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@ -414,7 +430,9 @@ module util_adxcvr #(
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input rx_4_p,
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input rx_4_p,
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input rx_4_n,
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input rx_4_n,
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output rx_out_clk_4,
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output rx_out_clk_4,
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output rx_out_clk_div2_4,
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input rx_clk_4,
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input rx_clk_4,
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input rx_clk_2x_4,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_4,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_4,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_4,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_4,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_4,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_4,
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@ -426,7 +444,9 @@ module util_adxcvr #(
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output tx_4_p,
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output tx_4_p,
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output tx_4_n,
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output tx_4_n,
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output tx_out_clk_4,
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output tx_out_clk_4,
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output tx_out_clk_div2_4,
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input tx_clk_4,
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input tx_clk_4,
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input tx_clk_2x_4,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_4,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_4,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_4,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_4,
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input [1:0] tx_header_4,
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input [1:0] tx_header_4,
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@ -488,7 +508,9 @@ module util_adxcvr #(
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input rx_5_p,
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input rx_5_p,
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input rx_5_n,
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input rx_5_n,
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output rx_out_clk_5,
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output rx_out_clk_5,
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output rx_out_clk_div2_5,
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input rx_clk_5,
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input rx_clk_5,
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input rx_clk_2x_5,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_5,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_5,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_5,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_5,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_5,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_5,
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@ -500,7 +522,9 @@ module util_adxcvr #(
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output tx_5_p,
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output tx_5_p,
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output tx_5_n,
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output tx_5_n,
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output tx_out_clk_5,
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output tx_out_clk_5,
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output tx_out_clk_div2_5,
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input tx_clk_5,
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input tx_clk_5,
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input tx_clk_2x_5,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_5,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_5,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_5,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_5,
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input [1:0] tx_header_5,
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input [1:0] tx_header_5,
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@ -556,7 +580,9 @@ module util_adxcvr #(
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input rx_6_p,
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input rx_6_p,
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input rx_6_n,
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input rx_6_n,
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output rx_out_clk_6,
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output rx_out_clk_6,
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output rx_out_clk_div2_6,
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input rx_clk_6,
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input rx_clk_6,
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input rx_clk_2x_6,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_6,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_6,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_6,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_6,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_6,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_6,
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@ -568,7 +594,9 @@ module util_adxcvr #(
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output tx_6_p,
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output tx_6_p,
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output tx_6_n,
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output tx_6_n,
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output tx_out_clk_6,
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output tx_out_clk_6,
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output tx_out_clk_div2_6,
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input tx_clk_6,
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input tx_clk_6,
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input tx_clk_2x_6,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_6,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_6,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_6,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_6,
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input [1:0] tx_header_6,
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input [1:0] tx_header_6,
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@ -624,7 +652,9 @@ module util_adxcvr #(
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input rx_7_p,
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input rx_7_p,
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input rx_7_n,
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input rx_7_n,
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output rx_out_clk_7,
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output rx_out_clk_7,
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output rx_out_clk_div2_7,
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input rx_clk_7,
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input rx_clk_7,
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input rx_clk_2x_7,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_7,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_7,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_7,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_7,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_7,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_7,
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@ -636,7 +666,9 @@ module util_adxcvr #(
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output tx_7_p,
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output tx_7_p,
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output tx_7_n,
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output tx_7_n,
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output tx_out_clk_7,
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output tx_out_clk_7,
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output tx_out_clk_div2_7,
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input tx_clk_7,
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input tx_clk_7,
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input tx_clk_2x_7,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_7,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_7,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_7,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_7,
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input [1:0] tx_header_7,
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input [1:0] tx_header_7,
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@ -694,7 +726,9 @@ module util_adxcvr #(
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input rx_8_p,
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input rx_8_p,
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input rx_8_n,
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input rx_8_n,
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output rx_out_clk_8,
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output rx_out_clk_8,
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output rx_out_clk_div2_8,
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input rx_clk_8,
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input rx_clk_8,
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input rx_clk_2x_8,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_8,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_8,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_8,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_8,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_8,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_8,
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@ -706,7 +740,9 @@ module util_adxcvr #(
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output tx_8_p,
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output tx_8_p,
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output tx_8_n,
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output tx_8_n,
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output tx_out_clk_8,
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output tx_out_clk_8,
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output tx_out_clk_div2_8,
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input tx_clk_8,
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input tx_clk_8,
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input tx_clk_2x_8,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_8,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_8,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_8,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_8,
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input [1:0] tx_header_8,
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input [1:0] tx_header_8,
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@ -768,7 +804,9 @@ module util_adxcvr #(
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input rx_9_p,
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input rx_9_p,
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input rx_9_n,
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input rx_9_n,
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output rx_out_clk_9,
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output rx_out_clk_9,
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output rx_out_clk_div2_9,
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input rx_clk_9,
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input rx_clk_9,
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input rx_clk_2x_9,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_9,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_9,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_9,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_9,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_9,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_9,
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@ -780,7 +818,9 @@ module util_adxcvr #(
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output tx_9_p,
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output tx_9_p,
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output tx_9_n,
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output tx_9_n,
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output tx_out_clk_9,
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output tx_out_clk_9,
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output tx_out_clk_div2_9,
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input tx_clk_9,
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input tx_clk_9,
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input tx_clk_2x_9,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_9,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_9,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_9,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_9,
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input [1:0] tx_header_9,
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input [1:0] tx_header_9,
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@ -836,7 +876,9 @@ module util_adxcvr #(
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input rx_10_p,
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input rx_10_p,
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input rx_10_n,
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input rx_10_n,
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output rx_out_clk_10,
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output rx_out_clk_10,
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output rx_out_clk_div2_10,
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input rx_clk_10,
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input rx_clk_10,
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input rx_clk_2x_10,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_10,
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output [DATA_PATH_WIDTH-1:0] rx_charisk_10,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_10,
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output [DATA_PATH_WIDTH-1:0] rx_disperr_10,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_10,
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output [DATA_PATH_WIDTH-1:0] rx_notintable_10,
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@ -848,7 +890,9 @@ module util_adxcvr #(
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output tx_10_p,
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output tx_10_p,
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output tx_10_n,
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output tx_10_n,
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output tx_out_clk_10,
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output tx_out_clk_10,
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output tx_out_clk_div2_10,
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input tx_clk_10,
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input tx_clk_10,
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input tx_clk_2x_10,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_10,
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input [DATA_PATH_WIDTH-1:0] tx_charisk_10,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_10,
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input [DATA_PATH_WIDTH*8-1:0] tx_data_10,
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input [1:0] tx_header_10,
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input [1:0] tx_header_10,
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@ -904,7 +948,9 @@ module util_adxcvr #(
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input rx_11_p,
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input rx_11_p,
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input rx_11_n,
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input rx_11_n,
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output rx_out_clk_11,
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output rx_out_clk_11,
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output rx_out_clk_div2_11,
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input rx_clk_11,
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input rx_clk_11,
|
||||||
|
input rx_clk_2x_11,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_charisk_11,
|
output [DATA_PATH_WIDTH-1:0] rx_charisk_11,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_disperr_11,
|
output [DATA_PATH_WIDTH-1:0] rx_disperr_11,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_notintable_11,
|
output [DATA_PATH_WIDTH-1:0] rx_notintable_11,
|
||||||
|
|
@ -916,7 +962,9 @@ module util_adxcvr #(
|
||||||
output tx_11_p,
|
output tx_11_p,
|
||||||
output tx_11_n,
|
output tx_11_n,
|
||||||
output tx_out_clk_11,
|
output tx_out_clk_11,
|
||||||
|
output tx_out_clk_div2_11,
|
||||||
input tx_clk_11,
|
input tx_clk_11,
|
||||||
|
input tx_clk_2x_11,
|
||||||
input [DATA_PATH_WIDTH-1:0] tx_charisk_11,
|
input [DATA_PATH_WIDTH-1:0] tx_charisk_11,
|
||||||
input [DATA_PATH_WIDTH*8-1:0] tx_data_11,
|
input [DATA_PATH_WIDTH*8-1:0] tx_data_11,
|
||||||
input [1:0] tx_header_11,
|
input [1:0] tx_header_11,
|
||||||
|
|
@ -974,7 +1022,9 @@ module util_adxcvr #(
|
||||||
input rx_12_p,
|
input rx_12_p,
|
||||||
input rx_12_n,
|
input rx_12_n,
|
||||||
output rx_out_clk_12,
|
output rx_out_clk_12,
|
||||||
|
output rx_out_clk_div2_12,
|
||||||
input rx_clk_12,
|
input rx_clk_12,
|
||||||
|
input rx_clk_2x_12,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_charisk_12,
|
output [DATA_PATH_WIDTH-1:0] rx_charisk_12,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_disperr_12,
|
output [DATA_PATH_WIDTH-1:0] rx_disperr_12,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_notintable_12,
|
output [DATA_PATH_WIDTH-1:0] rx_notintable_12,
|
||||||
|
|
@ -986,7 +1036,9 @@ module util_adxcvr #(
|
||||||
output tx_12_p,
|
output tx_12_p,
|
||||||
output tx_12_n,
|
output tx_12_n,
|
||||||
output tx_out_clk_12,
|
output tx_out_clk_12,
|
||||||
|
output tx_out_clk_div2_12,
|
||||||
input tx_clk_12,
|
input tx_clk_12,
|
||||||
|
input tx_clk_2x_12,
|
||||||
input [DATA_PATH_WIDTH-1:0] tx_charisk_12,
|
input [DATA_PATH_WIDTH-1:0] tx_charisk_12,
|
||||||
input [DATA_PATH_WIDTH*8-1:0] tx_data_12,
|
input [DATA_PATH_WIDTH*8-1:0] tx_data_12,
|
||||||
input [1:0] tx_header_12,
|
input [1:0] tx_header_12,
|
||||||
|
|
@ -1048,7 +1100,9 @@ module util_adxcvr #(
|
||||||
input rx_13_p,
|
input rx_13_p,
|
||||||
input rx_13_n,
|
input rx_13_n,
|
||||||
output rx_out_clk_13,
|
output rx_out_clk_13,
|
||||||
|
output rx_out_clk_div2_13,
|
||||||
input rx_clk_13,
|
input rx_clk_13,
|
||||||
|
input rx_clk_2x_13,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_charisk_13,
|
output [DATA_PATH_WIDTH-1:0] rx_charisk_13,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_disperr_13,
|
output [DATA_PATH_WIDTH-1:0] rx_disperr_13,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_notintable_13,
|
output [DATA_PATH_WIDTH-1:0] rx_notintable_13,
|
||||||
|
|
@ -1060,7 +1114,9 @@ module util_adxcvr #(
|
||||||
output tx_13_p,
|
output tx_13_p,
|
||||||
output tx_13_n,
|
output tx_13_n,
|
||||||
output tx_out_clk_13,
|
output tx_out_clk_13,
|
||||||
|
output tx_out_clk_div2_13,
|
||||||
input tx_clk_13,
|
input tx_clk_13,
|
||||||
|
input tx_clk_2x_13,
|
||||||
input [DATA_PATH_WIDTH-1:0] tx_charisk_13,
|
input [DATA_PATH_WIDTH-1:0] tx_charisk_13,
|
||||||
input [DATA_PATH_WIDTH*8-1:0] tx_data_13,
|
input [DATA_PATH_WIDTH*8-1:0] tx_data_13,
|
||||||
input [1:0] tx_header_13,
|
input [1:0] tx_header_13,
|
||||||
|
|
@ -1116,7 +1172,9 @@ module util_adxcvr #(
|
||||||
input rx_14_p,
|
input rx_14_p,
|
||||||
input rx_14_n,
|
input rx_14_n,
|
||||||
output rx_out_clk_14,
|
output rx_out_clk_14,
|
||||||
|
output rx_out_clk_div2_14,
|
||||||
input rx_clk_14,
|
input rx_clk_14,
|
||||||
|
input rx_clk_2x_14,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_charisk_14,
|
output [DATA_PATH_WIDTH-1:0] rx_charisk_14,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_disperr_14,
|
output [DATA_PATH_WIDTH-1:0] rx_disperr_14,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_notintable_14,
|
output [DATA_PATH_WIDTH-1:0] rx_notintable_14,
|
||||||
|
|
@ -1128,7 +1186,9 @@ module util_adxcvr #(
|
||||||
output tx_14_p,
|
output tx_14_p,
|
||||||
output tx_14_n,
|
output tx_14_n,
|
||||||
output tx_out_clk_14,
|
output tx_out_clk_14,
|
||||||
|
output tx_out_clk_div2_14,
|
||||||
input tx_clk_14,
|
input tx_clk_14,
|
||||||
|
input tx_clk_2x_14,
|
||||||
input [DATA_PATH_WIDTH-1:0] tx_charisk_14,
|
input [DATA_PATH_WIDTH-1:0] tx_charisk_14,
|
||||||
input [DATA_PATH_WIDTH*8-1:0] tx_data_14,
|
input [DATA_PATH_WIDTH*8-1:0] tx_data_14,
|
||||||
input [1:0] tx_header_14,
|
input [1:0] tx_header_14,
|
||||||
|
|
@ -1184,7 +1244,9 @@ module util_adxcvr #(
|
||||||
input rx_15_p,
|
input rx_15_p,
|
||||||
input rx_15_n,
|
input rx_15_n,
|
||||||
output rx_out_clk_15,
|
output rx_out_clk_15,
|
||||||
|
output rx_out_clk_div2_15,
|
||||||
input rx_clk_15,
|
input rx_clk_15,
|
||||||
|
input rx_clk_2x_15,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_charisk_15,
|
output [DATA_PATH_WIDTH-1:0] rx_charisk_15,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_disperr_15,
|
output [DATA_PATH_WIDTH-1:0] rx_disperr_15,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_notintable_15,
|
output [DATA_PATH_WIDTH-1:0] rx_notintable_15,
|
||||||
|
|
@ -1196,7 +1258,9 @@ module util_adxcvr #(
|
||||||
output tx_15_p,
|
output tx_15_p,
|
||||||
output tx_15_n,
|
output tx_15_n,
|
||||||
output tx_out_clk_15,
|
output tx_out_clk_15,
|
||||||
|
output tx_out_clk_div2_15,
|
||||||
input tx_clk_15,
|
input tx_clk_15,
|
||||||
|
input tx_clk_2x_15,
|
||||||
input [DATA_PATH_WIDTH-1:0] tx_charisk_15,
|
input [DATA_PATH_WIDTH-1:0] tx_charisk_15,
|
||||||
input [DATA_PATH_WIDTH*8-1:0] tx_data_15,
|
input [DATA_PATH_WIDTH*8-1:0] tx_data_15,
|
||||||
input [1:0] tx_header_15,
|
input [1:0] tx_header_15,
|
||||||
|
|
@ -1413,7 +1477,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_0_p),
|
.rx_p (rx_0_p),
|
||||||
.rx_n (rx_0_n),
|
.rx_n (rx_0_n),
|
||||||
.rx_out_clk (rx_out_clk_0),
|
.rx_out_clk (rx_out_clk_0),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_0),
|
||||||
.rx_clk (rx_clk_0),
|
.rx_clk (rx_clk_0),
|
||||||
|
.rx_clk_2x (rx_clk_2x_0),
|
||||||
.rx_charisk (rx_charisk_0),
|
.rx_charisk (rx_charisk_0),
|
||||||
.rx_disperr (rx_disperr_0),
|
.rx_disperr (rx_disperr_0),
|
||||||
.rx_notintable (rx_notintable_0),
|
.rx_notintable (rx_notintable_0),
|
||||||
|
|
@ -1424,7 +1490,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_0_p),
|
.tx_p (tx_0_p),
|
||||||
.tx_n (tx_0_n),
|
.tx_n (tx_0_n),
|
||||||
.tx_out_clk (tx_out_clk_0),
|
.tx_out_clk (tx_out_clk_0),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_0),
|
||||||
.tx_clk (tx_clk_0),
|
.tx_clk (tx_clk_0),
|
||||||
|
.tx_clk_2x (tx_clk_2x_0),
|
||||||
.tx_charisk (tx_charisk_0),
|
.tx_charisk (tx_charisk_0),
|
||||||
.tx_data (tx_data_0),
|
.tx_data (tx_data_0),
|
||||||
.tx_header (tx_header_0),
|
.tx_header (tx_header_0),
|
||||||
|
|
@ -1558,7 +1626,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_1_p),
|
.rx_p (rx_1_p),
|
||||||
.rx_n (rx_1_n),
|
.rx_n (rx_1_n),
|
||||||
.rx_out_clk (rx_out_clk_1),
|
.rx_out_clk (rx_out_clk_1),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_1),
|
||||||
.rx_clk (rx_clk_1),
|
.rx_clk (rx_clk_1),
|
||||||
|
.rx_clk_2x (rx_clk_2x_1),
|
||||||
.rx_charisk (rx_charisk_1),
|
.rx_charisk (rx_charisk_1),
|
||||||
.rx_disperr (rx_disperr_1),
|
.rx_disperr (rx_disperr_1),
|
||||||
.rx_notintable (rx_notintable_1),
|
.rx_notintable (rx_notintable_1),
|
||||||
|
|
@ -1569,7 +1639,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_1_p),
|
.tx_p (tx_1_p),
|
||||||
.tx_n (tx_1_n),
|
.tx_n (tx_1_n),
|
||||||
.tx_out_clk (tx_out_clk_1),
|
.tx_out_clk (tx_out_clk_1),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_1),
|
||||||
.tx_clk (tx_clk_1),
|
.tx_clk (tx_clk_1),
|
||||||
|
.tx_clk_2x (tx_clk_2x_1),
|
||||||
.tx_charisk (tx_charisk_1),
|
.tx_charisk (tx_charisk_1),
|
||||||
.tx_data (tx_data_1),
|
.tx_data (tx_data_1),
|
||||||
.tx_header (tx_header_1),
|
.tx_header (tx_header_1),
|
||||||
|
|
@ -1703,7 +1775,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_2_p),
|
.rx_p (rx_2_p),
|
||||||
.rx_n (rx_2_n),
|
.rx_n (rx_2_n),
|
||||||
.rx_out_clk (rx_out_clk_2),
|
.rx_out_clk (rx_out_clk_2),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_2),
|
||||||
.rx_clk (rx_clk_2),
|
.rx_clk (rx_clk_2),
|
||||||
|
.rx_clk_2x (rx_clk_2x_2),
|
||||||
.rx_charisk (rx_charisk_2),
|
.rx_charisk (rx_charisk_2),
|
||||||
.rx_disperr (rx_disperr_2),
|
.rx_disperr (rx_disperr_2),
|
||||||
.rx_notintable (rx_notintable_2),
|
.rx_notintable (rx_notintable_2),
|
||||||
|
|
@ -1714,7 +1788,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_2_p),
|
.tx_p (tx_2_p),
|
||||||
.tx_n (tx_2_n),
|
.tx_n (tx_2_n),
|
||||||
.tx_out_clk (tx_out_clk_2),
|
.tx_out_clk (tx_out_clk_2),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_2),
|
||||||
.tx_clk (tx_clk_2),
|
.tx_clk (tx_clk_2),
|
||||||
|
.tx_clk_2x (tx_clk_2x_2),
|
||||||
.tx_charisk (tx_charisk_2),
|
.tx_charisk (tx_charisk_2),
|
||||||
.tx_data (tx_data_2),
|
.tx_data (tx_data_2),
|
||||||
.tx_header (tx_header_2),
|
.tx_header (tx_header_2),
|
||||||
|
|
@ -1848,7 +1924,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_3_p),
|
.rx_p (rx_3_p),
|
||||||
.rx_n (rx_3_n),
|
.rx_n (rx_3_n),
|
||||||
.rx_out_clk (rx_out_clk_3),
|
.rx_out_clk (rx_out_clk_3),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_3),
|
||||||
.rx_clk (rx_clk_3),
|
.rx_clk (rx_clk_3),
|
||||||
|
.rx_clk_2x (rx_clk_2x_3),
|
||||||
.rx_charisk (rx_charisk_3),
|
.rx_charisk (rx_charisk_3),
|
||||||
.rx_disperr (rx_disperr_3),
|
.rx_disperr (rx_disperr_3),
|
||||||
.rx_notintable (rx_notintable_3),
|
.rx_notintable (rx_notintable_3),
|
||||||
|
|
@ -1859,7 +1937,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_3_p),
|
.tx_p (tx_3_p),
|
||||||
.tx_n (tx_3_n),
|
.tx_n (tx_3_n),
|
||||||
.tx_out_clk (tx_out_clk_3),
|
.tx_out_clk (tx_out_clk_3),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_3),
|
||||||
.tx_clk (tx_clk_3),
|
.tx_clk (tx_clk_3),
|
||||||
|
.tx_clk_2x (tx_clk_2x_3),
|
||||||
.tx_charisk (tx_charisk_3),
|
.tx_charisk (tx_charisk_3),
|
||||||
.tx_data (tx_data_3),
|
.tx_data (tx_data_3),
|
||||||
.tx_header (tx_header_3),
|
.tx_header (tx_header_3),
|
||||||
|
|
@ -2043,7 +2123,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_4_p),
|
.rx_p (rx_4_p),
|
||||||
.rx_n (rx_4_n),
|
.rx_n (rx_4_n),
|
||||||
.rx_out_clk (rx_out_clk_4),
|
.rx_out_clk (rx_out_clk_4),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_4),
|
||||||
.rx_clk (rx_clk_4),
|
.rx_clk (rx_clk_4),
|
||||||
|
.rx_clk_2x (rx_clk_2x_4),
|
||||||
.rx_charisk (rx_charisk_4),
|
.rx_charisk (rx_charisk_4),
|
||||||
.rx_disperr (rx_disperr_4),
|
.rx_disperr (rx_disperr_4),
|
||||||
.rx_notintable (rx_notintable_4),
|
.rx_notintable (rx_notintable_4),
|
||||||
|
|
@ -2054,7 +2136,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_4_p),
|
.tx_p (tx_4_p),
|
||||||
.tx_n (tx_4_n),
|
.tx_n (tx_4_n),
|
||||||
.tx_out_clk (tx_out_clk_4),
|
.tx_out_clk (tx_out_clk_4),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_4),
|
||||||
.tx_clk (tx_clk_4),
|
.tx_clk (tx_clk_4),
|
||||||
|
.tx_clk_2x (tx_clk_2x_4),
|
||||||
.tx_charisk (tx_charisk_4),
|
.tx_charisk (tx_charisk_4),
|
||||||
.tx_data (tx_data_4),
|
.tx_data (tx_data_4),
|
||||||
.tx_header (tx_header_4),
|
.tx_header (tx_header_4),
|
||||||
|
|
@ -2188,7 +2272,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_5_p),
|
.rx_p (rx_5_p),
|
||||||
.rx_n (rx_5_n),
|
.rx_n (rx_5_n),
|
||||||
.rx_out_clk (rx_out_clk_5),
|
.rx_out_clk (rx_out_clk_5),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_5),
|
||||||
.rx_clk (rx_clk_5),
|
.rx_clk (rx_clk_5),
|
||||||
|
.rx_clk_2x (rx_clk_2x_5),
|
||||||
.rx_charisk (rx_charisk_5),
|
.rx_charisk (rx_charisk_5),
|
||||||
.rx_disperr (rx_disperr_5),
|
.rx_disperr (rx_disperr_5),
|
||||||
.rx_notintable (rx_notintable_5),
|
.rx_notintable (rx_notintable_5),
|
||||||
|
|
@ -2199,7 +2285,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_5_p),
|
.tx_p (tx_5_p),
|
||||||
.tx_n (tx_5_n),
|
.tx_n (tx_5_n),
|
||||||
.tx_out_clk (tx_out_clk_5),
|
.tx_out_clk (tx_out_clk_5),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_5),
|
||||||
.tx_clk (tx_clk_5),
|
.tx_clk (tx_clk_5),
|
||||||
|
.tx_clk_2x (tx_clk_2x_5),
|
||||||
.tx_charisk (tx_charisk_5),
|
.tx_charisk (tx_charisk_5),
|
||||||
.tx_data (tx_data_5),
|
.tx_data (tx_data_5),
|
||||||
.tx_header (tx_header_5),
|
.tx_header (tx_header_5),
|
||||||
|
|
@ -2333,7 +2421,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_6_p),
|
.rx_p (rx_6_p),
|
||||||
.rx_n (rx_6_n),
|
.rx_n (rx_6_n),
|
||||||
.rx_out_clk (rx_out_clk_6),
|
.rx_out_clk (rx_out_clk_6),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_6),
|
||||||
.rx_clk (rx_clk_6),
|
.rx_clk (rx_clk_6),
|
||||||
|
.rx_clk_2x (rx_clk_2x_6),
|
||||||
.rx_charisk (rx_charisk_6),
|
.rx_charisk (rx_charisk_6),
|
||||||
.rx_disperr (rx_disperr_6),
|
.rx_disperr (rx_disperr_6),
|
||||||
.rx_notintable (rx_notintable_6),
|
.rx_notintable (rx_notintable_6),
|
||||||
|
|
@ -2344,7 +2434,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_6_p),
|
.tx_p (tx_6_p),
|
||||||
.tx_n (tx_6_n),
|
.tx_n (tx_6_n),
|
||||||
.tx_out_clk (tx_out_clk_6),
|
.tx_out_clk (tx_out_clk_6),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_6),
|
||||||
.tx_clk (tx_clk_6),
|
.tx_clk (tx_clk_6),
|
||||||
|
.tx_clk_2x (tx_clk_2x_6),
|
||||||
.tx_charisk (tx_charisk_6),
|
.tx_charisk (tx_charisk_6),
|
||||||
.tx_data (tx_data_6),
|
.tx_data (tx_data_6),
|
||||||
.tx_header (tx_header_6),
|
.tx_header (tx_header_6),
|
||||||
|
|
@ -2478,7 +2570,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_7_p),
|
.rx_p (rx_7_p),
|
||||||
.rx_n (rx_7_n),
|
.rx_n (rx_7_n),
|
||||||
.rx_out_clk (rx_out_clk_7),
|
.rx_out_clk (rx_out_clk_7),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_7),
|
||||||
.rx_clk (rx_clk_7),
|
.rx_clk (rx_clk_7),
|
||||||
|
.rx_clk_2x (rx_clk_2x_7),
|
||||||
.rx_charisk (rx_charisk_7),
|
.rx_charisk (rx_charisk_7),
|
||||||
.rx_disperr (rx_disperr_7),
|
.rx_disperr (rx_disperr_7),
|
||||||
.rx_notintable (rx_notintable_7),
|
.rx_notintable (rx_notintable_7),
|
||||||
|
|
@ -2489,7 +2583,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_7_p),
|
.tx_p (tx_7_p),
|
||||||
.tx_n (tx_7_n),
|
.tx_n (tx_7_n),
|
||||||
.tx_out_clk (tx_out_clk_7),
|
.tx_out_clk (tx_out_clk_7),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_7),
|
||||||
.tx_clk (tx_clk_7),
|
.tx_clk (tx_clk_7),
|
||||||
|
.tx_clk_2x (tx_clk_2x_7),
|
||||||
.tx_charisk (tx_charisk_7),
|
.tx_charisk (tx_charisk_7),
|
||||||
.tx_data (tx_data_7),
|
.tx_data (tx_data_7),
|
||||||
.tx_header (tx_header_7),
|
.tx_header (tx_header_7),
|
||||||
|
|
@ -2673,7 +2769,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_8_p),
|
.rx_p (rx_8_p),
|
||||||
.rx_n (rx_8_n),
|
.rx_n (rx_8_n),
|
||||||
.rx_out_clk (rx_out_clk_8),
|
.rx_out_clk (rx_out_clk_8),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_8),
|
||||||
.rx_clk (rx_clk_8),
|
.rx_clk (rx_clk_8),
|
||||||
|
.rx_clk_2x (rx_clk_2x_8),
|
||||||
.rx_charisk (rx_charisk_8),
|
.rx_charisk (rx_charisk_8),
|
||||||
.rx_disperr (rx_disperr_8),
|
.rx_disperr (rx_disperr_8),
|
||||||
.rx_notintable (rx_notintable_8),
|
.rx_notintable (rx_notintable_8),
|
||||||
|
|
@ -2684,7 +2782,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_8_p),
|
.tx_p (tx_8_p),
|
||||||
.tx_n (tx_8_n),
|
.tx_n (tx_8_n),
|
||||||
.tx_out_clk (tx_out_clk_8),
|
.tx_out_clk (tx_out_clk_8),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_8),
|
||||||
.tx_clk (tx_clk_8),
|
.tx_clk (tx_clk_8),
|
||||||
|
.tx_clk_2x (tx_clk_2x_8),
|
||||||
.tx_charisk (tx_charisk_8),
|
.tx_charisk (tx_charisk_8),
|
||||||
.tx_data (tx_data_8),
|
.tx_data (tx_data_8),
|
||||||
.tx_header (tx_header_8),
|
.tx_header (tx_header_8),
|
||||||
|
|
@ -2818,7 +2918,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_9_p),
|
.rx_p (rx_9_p),
|
||||||
.rx_n (rx_9_n),
|
.rx_n (rx_9_n),
|
||||||
.rx_out_clk (rx_out_clk_9),
|
.rx_out_clk (rx_out_clk_9),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_9),
|
||||||
.rx_clk (rx_clk_9),
|
.rx_clk (rx_clk_9),
|
||||||
|
.rx_clk_2x (rx_clk_2x_9),
|
||||||
.rx_charisk (rx_charisk_9),
|
.rx_charisk (rx_charisk_9),
|
||||||
.rx_disperr (rx_disperr_9),
|
.rx_disperr (rx_disperr_9),
|
||||||
.rx_notintable (rx_notintable_9),
|
.rx_notintable (rx_notintable_9),
|
||||||
|
|
@ -2829,7 +2931,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_9_p),
|
.tx_p (tx_9_p),
|
||||||
.tx_n (tx_9_n),
|
.tx_n (tx_9_n),
|
||||||
.tx_out_clk (tx_out_clk_9),
|
.tx_out_clk (tx_out_clk_9),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_9),
|
||||||
.tx_clk (tx_clk_9),
|
.tx_clk (tx_clk_9),
|
||||||
|
.tx_clk_2x (tx_clk_2x_9),
|
||||||
.tx_charisk (tx_charisk_9),
|
.tx_charisk (tx_charisk_9),
|
||||||
.tx_data (tx_data_9),
|
.tx_data (tx_data_9),
|
||||||
.tx_header (tx_header_9),
|
.tx_header (tx_header_9),
|
||||||
|
|
@ -2963,7 +3067,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_10_p),
|
.rx_p (rx_10_p),
|
||||||
.rx_n (rx_10_n),
|
.rx_n (rx_10_n),
|
||||||
.rx_out_clk (rx_out_clk_10),
|
.rx_out_clk (rx_out_clk_10),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_10),
|
||||||
.rx_clk (rx_clk_10),
|
.rx_clk (rx_clk_10),
|
||||||
|
.rx_clk_2x (rx_clk_2x_10),
|
||||||
.rx_charisk (rx_charisk_10),
|
.rx_charisk (rx_charisk_10),
|
||||||
.rx_disperr (rx_disperr_10),
|
.rx_disperr (rx_disperr_10),
|
||||||
.rx_notintable (rx_notintable_10),
|
.rx_notintable (rx_notintable_10),
|
||||||
|
|
@ -2974,7 +3080,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_10_p),
|
.tx_p (tx_10_p),
|
||||||
.tx_n (tx_10_n),
|
.tx_n (tx_10_n),
|
||||||
.tx_out_clk (tx_out_clk_10),
|
.tx_out_clk (tx_out_clk_10),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_10),
|
||||||
.tx_clk (tx_clk_10),
|
.tx_clk (tx_clk_10),
|
||||||
|
.tx_clk_2x (tx_clk_2x_10),
|
||||||
.tx_charisk (tx_charisk_10),
|
.tx_charisk (tx_charisk_10),
|
||||||
.tx_data (tx_data_10),
|
.tx_data (tx_data_10),
|
||||||
.tx_header (tx_header_10),
|
.tx_header (tx_header_10),
|
||||||
|
|
@ -3108,7 +3216,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_11_p),
|
.rx_p (rx_11_p),
|
||||||
.rx_n (rx_11_n),
|
.rx_n (rx_11_n),
|
||||||
.rx_out_clk (rx_out_clk_11),
|
.rx_out_clk (rx_out_clk_11),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_11),
|
||||||
.rx_clk (rx_clk_11),
|
.rx_clk (rx_clk_11),
|
||||||
|
.rx_clk_2x (rx_clk_2x_11),
|
||||||
.rx_charisk (rx_charisk_11),
|
.rx_charisk (rx_charisk_11),
|
||||||
.rx_disperr (rx_disperr_11),
|
.rx_disperr (rx_disperr_11),
|
||||||
.rx_notintable (rx_notintable_11),
|
.rx_notintable (rx_notintable_11),
|
||||||
|
|
@ -3119,7 +3229,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_11_p),
|
.tx_p (tx_11_p),
|
||||||
.tx_n (tx_11_n),
|
.tx_n (tx_11_n),
|
||||||
.tx_out_clk (tx_out_clk_11),
|
.tx_out_clk (tx_out_clk_11),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_11),
|
||||||
.tx_clk (tx_clk_11),
|
.tx_clk (tx_clk_11),
|
||||||
|
.tx_clk_2x (tx_clk_2x_11),
|
||||||
.tx_charisk (tx_charisk_11),
|
.tx_charisk (tx_charisk_11),
|
||||||
.tx_data (tx_data_11),
|
.tx_data (tx_data_11),
|
||||||
.tx_header (tx_header_11),
|
.tx_header (tx_header_11),
|
||||||
|
|
@ -3303,7 +3415,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_12_p),
|
.rx_p (rx_12_p),
|
||||||
.rx_n (rx_12_n),
|
.rx_n (rx_12_n),
|
||||||
.rx_out_clk (rx_out_clk_12),
|
.rx_out_clk (rx_out_clk_12),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_12),
|
||||||
.rx_clk (rx_clk_12),
|
.rx_clk (rx_clk_12),
|
||||||
|
.rx_clk_2x (rx_clk_2x_12),
|
||||||
.rx_charisk (rx_charisk_12),
|
.rx_charisk (rx_charisk_12),
|
||||||
.rx_disperr (rx_disperr_12),
|
.rx_disperr (rx_disperr_12),
|
||||||
.rx_notintable (rx_notintable_12),
|
.rx_notintable (rx_notintable_12),
|
||||||
|
|
@ -3314,7 +3428,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_12_p),
|
.tx_p (tx_12_p),
|
||||||
.tx_n (tx_12_n),
|
.tx_n (tx_12_n),
|
||||||
.tx_out_clk (tx_out_clk_12),
|
.tx_out_clk (tx_out_clk_12),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_12),
|
||||||
.tx_clk (tx_clk_12),
|
.tx_clk (tx_clk_12),
|
||||||
|
.tx_clk_2x (tx_clk_2x_12),
|
||||||
.tx_charisk (tx_charisk_12),
|
.tx_charisk (tx_charisk_12),
|
||||||
.tx_data (tx_data_12),
|
.tx_data (tx_data_12),
|
||||||
.tx_header (tx_header_12),
|
.tx_header (tx_header_12),
|
||||||
|
|
@ -3448,7 +3564,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_13_p),
|
.rx_p (rx_13_p),
|
||||||
.rx_n (rx_13_n),
|
.rx_n (rx_13_n),
|
||||||
.rx_out_clk (rx_out_clk_13),
|
.rx_out_clk (rx_out_clk_13),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_13),
|
||||||
.rx_clk (rx_clk_13),
|
.rx_clk (rx_clk_13),
|
||||||
|
.rx_clk_2x (rx_clk_2x_13),
|
||||||
.rx_charisk (rx_charisk_13),
|
.rx_charisk (rx_charisk_13),
|
||||||
.rx_disperr (rx_disperr_13),
|
.rx_disperr (rx_disperr_13),
|
||||||
.rx_notintable (rx_notintable_13),
|
.rx_notintable (rx_notintable_13),
|
||||||
|
|
@ -3459,7 +3577,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_13_p),
|
.tx_p (tx_13_p),
|
||||||
.tx_n (tx_13_n),
|
.tx_n (tx_13_n),
|
||||||
.tx_out_clk (tx_out_clk_13),
|
.tx_out_clk (tx_out_clk_13),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_13),
|
||||||
.tx_clk (tx_clk_13),
|
.tx_clk (tx_clk_13),
|
||||||
|
.tx_clk_2x (tx_clk_2x_13),
|
||||||
.tx_charisk (tx_charisk_13),
|
.tx_charisk (tx_charisk_13),
|
||||||
.tx_data (tx_data_13),
|
.tx_data (tx_data_13),
|
||||||
.tx_header (tx_header_13),
|
.tx_header (tx_header_13),
|
||||||
|
|
@ -3593,7 +3713,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_14_p),
|
.rx_p (rx_14_p),
|
||||||
.rx_n (rx_14_n),
|
.rx_n (rx_14_n),
|
||||||
.rx_out_clk (rx_out_clk_14),
|
.rx_out_clk (rx_out_clk_14),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_14),
|
||||||
.rx_clk (rx_clk_14),
|
.rx_clk (rx_clk_14),
|
||||||
|
.rx_clk_2x (rx_clk_2x_14),
|
||||||
.rx_charisk (rx_charisk_14),
|
.rx_charisk (rx_charisk_14),
|
||||||
.rx_disperr (rx_disperr_14),
|
.rx_disperr (rx_disperr_14),
|
||||||
.rx_notintable (rx_notintable_14),
|
.rx_notintable (rx_notintable_14),
|
||||||
|
|
@ -3604,7 +3726,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_14_p),
|
.tx_p (tx_14_p),
|
||||||
.tx_n (tx_14_n),
|
.tx_n (tx_14_n),
|
||||||
.tx_out_clk (tx_out_clk_14),
|
.tx_out_clk (tx_out_clk_14),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_14),
|
||||||
.tx_clk (tx_clk_14),
|
.tx_clk (tx_clk_14),
|
||||||
|
.tx_clk_2x (tx_clk_2x_14),
|
||||||
.tx_charisk (tx_charisk_14),
|
.tx_charisk (tx_charisk_14),
|
||||||
.tx_data (tx_data_14),
|
.tx_data (tx_data_14),
|
||||||
.tx_header (tx_header_14),
|
.tx_header (tx_header_14),
|
||||||
|
|
@ -3738,7 +3862,9 @@ module util_adxcvr #(
|
||||||
.rx_p (rx_15_p),
|
.rx_p (rx_15_p),
|
||||||
.rx_n (rx_15_n),
|
.rx_n (rx_15_n),
|
||||||
.rx_out_clk (rx_out_clk_15),
|
.rx_out_clk (rx_out_clk_15),
|
||||||
|
.rx_out_clk_div2 (rx_out_clk_div2_15),
|
||||||
.rx_clk (rx_clk_15),
|
.rx_clk (rx_clk_15),
|
||||||
|
.rx_clk_2x (rx_clk_2x_15),
|
||||||
.rx_charisk (rx_charisk_15),
|
.rx_charisk (rx_charisk_15),
|
||||||
.rx_disperr (rx_disperr_15),
|
.rx_disperr (rx_disperr_15),
|
||||||
.rx_notintable (rx_notintable_15),
|
.rx_notintable (rx_notintable_15),
|
||||||
|
|
@ -3749,7 +3875,9 @@ module util_adxcvr #(
|
||||||
.tx_p (tx_15_p),
|
.tx_p (tx_15_p),
|
||||||
.tx_n (tx_15_n),
|
.tx_n (tx_15_n),
|
||||||
.tx_out_clk (tx_out_clk_15),
|
.tx_out_clk (tx_out_clk_15),
|
||||||
|
.tx_out_clk_div2 (tx_out_clk_div2_15),
|
||||||
.tx_clk (tx_clk_15),
|
.tx_clk (tx_clk_15),
|
||||||
|
.tx_clk_2x (tx_clk_2x_15),
|
||||||
.tx_charisk (tx_charisk_15),
|
.tx_charisk (tx_charisk_15),
|
||||||
.tx_data (tx_data_15),
|
.tx_data (tx_data_15),
|
||||||
.tx_header (tx_header_15),
|
.tx_header (tx_header_15),
|
||||||
|
|
|
||||||
|
|
@ -163,6 +163,12 @@ ipx::infer_bus_interface tx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current
|
||||||
ipx::infer_bus_interface tx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
ipx::infer_bus_interface tx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
ipx::infer_bus_interface tx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
ipx::infer_bus_interface tx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
|
|
||||||
|
for {set n 0} {$n < 16} {incr n} {
|
||||||
|
ipx::infer_bus_interface rx_clk_2x_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
|
ipx::infer_bus_interface tx_clk_2x_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
|
ipx::infer_bus_interface rx_out_clk_div2_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
|
ipx::infer_bus_interface tx_out_clk_div2_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||||
|
}
|
||||||
ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||||
|
|
||||||
ipx::infer_bus_interface up_rx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
ipx::infer_bus_interface up_rx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||||
|
|
@ -315,7 +321,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
||||||
[ipx::get_ports rx_*0* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_0_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_0 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_0 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_0 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
|
||||||
[ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -327,7 +336,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
||||||
[ipx::get_ports tx_*0* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_0* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_0 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_0 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
|
||||||
[ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -338,6 +349,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_0 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_0 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_0 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_0 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency \
|
set_property enablement_dependency \
|
||||||
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
|
||||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
|
||||||
|
|
@ -359,7 +386,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
||||||
[ipx::get_ports rx_*1* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_1_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_1 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_1 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_1 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
|
||||||
[ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -371,7 +401,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
||||||
[ipx::get_ports tx_*1* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_1* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_1 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_1 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
|
||||||
[ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -382,6 +414,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_1 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_1 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_1 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_1 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
||||||
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -392,7 +440,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
||||||
[ipx::get_ports rx_*2* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_2_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_2 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_2 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_2 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
|
||||||
[ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -404,7 +455,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
||||||
[ipx::get_ports tx_*2* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_2* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_2 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_2 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
|
||||||
[ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -415,6 +468,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_2 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_2 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_2 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_2 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
||||||
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -425,7 +494,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
||||||
[ipx::get_ports rx_*3* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_3_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_3 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_3 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_3 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
|
||||||
[ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -437,7 +509,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
||||||
[ipx::get_ports tx_*3* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_3* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_3 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_3 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
|
||||||
[ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -448,6 +522,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_3 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_3 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_3 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_3 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
||||||
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -458,7 +548,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
||||||
[ipx::get_ports rx_*4* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_4_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_4 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_4 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_4 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
|
||||||
[ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -470,7 +563,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
||||||
[ipx::get_ports tx_*4* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_4* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_4 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_4 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
|
||||||
[ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -481,6 +576,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_4 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_4 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_4 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_4 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency \
|
set_property enablement_dependency \
|
||||||
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
|
||||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
|
||||||
|
|
@ -502,7 +613,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
||||||
[ipx::get_ports rx_*5* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_5_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_5 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_5 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_5 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
|
||||||
[ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -514,7 +628,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
||||||
[ipx::get_ports tx_*5* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_5* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_5 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_5 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
|
||||||
[ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -525,6 +641,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_5 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_5 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_5 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_5 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
||||||
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -535,7 +667,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
||||||
[ipx::get_ports rx_*6* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_6_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_6 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_6 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_6 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
|
||||||
[ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -547,7 +682,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
||||||
[ipx::get_ports tx_*6* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_6* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_6 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_6 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
|
||||||
[ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -558,6 +695,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_6 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_6 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_6 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_6 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
||||||
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -568,7 +721,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
||||||
[ipx::get_ports rx_*7* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_7_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_7 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_7 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_7 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
|
||||||
[ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -580,7 +736,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
||||||
[ipx::get_ports tx_*7* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_7* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_7 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_7 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
|
||||||
[ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -591,6 +749,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_7 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_7 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_7 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_7 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
||||||
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -601,7 +775,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
||||||
[ipx::get_ports rx_*8* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_8_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_8 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_8 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_8 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
|
||||||
[ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -613,7 +790,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
||||||
[ipx::get_ports tx_*8* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_8* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_8 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_8 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
|
||||||
[ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -624,6 +803,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_8 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_8 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_8 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_8 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency \
|
set_property enablement_dependency \
|
||||||
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
|
||||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
|
||||||
|
|
@ -645,7 +840,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
||||||
[ipx::get_ports rx_*9* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_9_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_9 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_9 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_9 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
|
||||||
[ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -657,7 +855,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
||||||
[ipx::get_ports tx_*9* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_9* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_9 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_9 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
|
||||||
[ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -668,6 +868,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_9 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_9 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_9 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_9 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
||||||
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -678,7 +894,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
||||||
[ipx::get_ports rx_*10* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_10_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_10 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_10 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_10 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
|
||||||
[ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -690,7 +909,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
||||||
[ipx::get_ports tx_*10* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_10* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_10 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_10 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
|
||||||
[ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -701,6 +922,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_10 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_10 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_10 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_10 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
||||||
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -711,7 +948,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
||||||
[ipx::get_ports rx_*11* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_11_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_11 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_11 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_11 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
|
||||||
[ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -723,7 +963,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
||||||
[ipx::get_ports tx_*11* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_11* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_11 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_11 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
|
||||||
[ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -734,6 +976,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_11 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_11 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_11 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_11 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
||||||
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -744,7 +1002,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
||||||
[ipx::get_ports rx_*12* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_12_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_12 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_12 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_12 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
|
||||||
[ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -756,7 +1017,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
||||||
[ipx::get_ports tx_*12* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_12* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_12 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_12 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
|
||||||
[ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -767,6 +1030,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_12 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_12 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_12 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_12 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency \
|
set_property enablement_dependency \
|
||||||
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
|
||||||
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
|
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
|
||||||
|
|
@ -788,7 +1067,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
||||||
[ipx::get_ports rx_*13* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_13_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_13 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_13 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_13 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
|
||||||
[ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -800,7 +1082,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
||||||
[ipx::get_ports tx_*13* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_13* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_13 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_13 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
|
||||||
[ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -811,6 +1095,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_13 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_13 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_13 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_13 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
||||||
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -821,7 +1121,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
||||||
[ipx::get_ports rx_*14* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_14_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_14 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_14 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_14 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
|
||||||
[ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -833,7 +1136,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
||||||
[ipx::get_ports tx_*14* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_14* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_14 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_14 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
|
||||||
[ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -844,6 +1149,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_14 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_14 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_14 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_14 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
||||||
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
|
@ -854,7 +1175,10 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF
|
||||||
[ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
||||||
[ipx::get_ports rx_*15* -of_objects [ipx::current_core]]
|
[ipx::get_ports rx_15_* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_clk_15 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_calign_15 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_15 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
|
||||||
[ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -866,7 +1190,9 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF
|
||||||
[ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]]
|
[ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
||||||
[ipx::get_ports tx_*15* -of_objects [ipx::current_core]]
|
[ipx::get_ports tx_15* -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_clk_15 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_15 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
|
||||||
[ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \
|
[ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \
|
||||||
|
|
@ -877,6 +1203,22 @@ set_property enablement_dependency \
|
||||||
[ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \
|
[ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \
|
||||||
[ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]]
|
[ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]]
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports rx_clk_2x_15 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports rx_out_clk_div2_15 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
|
set_property enablement_dependency \
|
||||||
|
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) and \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \
|
||||||
|
((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \
|
||||||
|
(spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \
|
||||||
|
[ipx::get_ports tx_clk_2x_15 -of_objects [ipx::current_core]] \
|
||||||
|
[ipx::get_ports tx_out_clk_div2_15 -of_objects [ipx::current_core]] \
|
||||||
|
|
||||||
adi_add_auto_fpga_spec_params
|
adi_add_auto_fpga_spec_params
|
||||||
set cc [ipx::current_core]
|
set cc [ipx::current_core]
|
||||||
set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc]
|
set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc]
|
||||||
|
|
|
||||||
|
|
@ -110,7 +110,9 @@ module util_adxcvr_xch #(
|
||||||
input rx_n,
|
input rx_n,
|
||||||
|
|
||||||
output rx_out_clk,
|
output rx_out_clk,
|
||||||
|
output rx_out_clk_div2,
|
||||||
input rx_clk,
|
input rx_clk,
|
||||||
|
input rx_clk_2x,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_charisk,
|
output [DATA_PATH_WIDTH-1:0] rx_charisk,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_disperr,
|
output [DATA_PATH_WIDTH-1:0] rx_disperr,
|
||||||
output [DATA_PATH_WIDTH-1:0] rx_notintable,
|
output [DATA_PATH_WIDTH-1:0] rx_notintable,
|
||||||
|
|
@ -125,7 +127,9 @@ module util_adxcvr_xch #(
|
||||||
output tx_n,
|
output tx_n,
|
||||||
|
|
||||||
output tx_out_clk,
|
output tx_out_clk,
|
||||||
|
output tx_out_clk_div2,
|
||||||
input tx_clk,
|
input tx_clk,
|
||||||
|
input tx_clk_2x,
|
||||||
input [DATA_PATH_WIDTH-1:0] tx_charisk,
|
input [DATA_PATH_WIDTH-1:0] tx_charisk,
|
||||||
input [DATA_PATH_WIDTH*8-1:0] tx_data,
|
input [DATA_PATH_WIDTH*8-1:0] tx_data,
|
||||||
input [1:0] tx_header,
|
input [1:0] tx_header,
|
||||||
|
|
@ -224,6 +228,10 @@ module util_adxcvr_xch #(
|
||||||
wire [ 3:0] rx_notintable_open_s;
|
wire [ 3:0] rx_notintable_open_s;
|
||||||
wire [95:0] rx_data_open_s;
|
wire [95:0] rx_data_open_s;
|
||||||
wire cpll_locked_s;
|
wire cpll_locked_s;
|
||||||
|
wire rx_usrclk;
|
||||||
|
wire rx_usrclk2;
|
||||||
|
wire tx_usrclk;
|
||||||
|
wire tx_usrclk2;
|
||||||
|
|
||||||
// pll
|
// pll
|
||||||
|
|
||||||
|
|
@ -395,23 +403,23 @@ module util_adxcvr_xch #(
|
||||||
localparam RX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40;
|
localparam RX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40;
|
||||||
localparam TX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40;
|
localparam TX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40;
|
||||||
localparam GEARBOX_MODE = LINK_MODE[1] ? 5'b10001 : 5'b00000;
|
localparam GEARBOX_MODE = LINK_MODE[1] ? 5'b10001 : 5'b00000;
|
||||||
localparam GEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE";
|
localparam RXGEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE";
|
||||||
|
localparam TXGEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE";
|
||||||
localparam RX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1;
|
localparam RX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1;
|
||||||
localparam TX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1;
|
localparam TX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1;
|
||||||
localparam RX8B10BEN = LINK_MODE[1] ? 0 : 1;
|
localparam RX8B10BEN = LINK_MODE[1] ? 0 : 1;
|
||||||
localparam TX8B10BEN = LINK_MODE[1] ? 0 : 1;
|
localparam TX8B10BEN = LINK_MODE[1] ? 0 : 1;
|
||||||
localparam TX_RXDETECT_CFG = LINK_MODE[1] ? 14'h032 : 14'b00000000110010;
|
|
||||||
localparam RXGBOX_FIFO_INIT_RD_ADDR = LINK_MODE[1] ? 3 : 4;
|
localparam RXGBOX_FIFO_INIT_RD_ADDR = LINK_MODE[1] ? 3 : 4;
|
||||||
localparam RXBUF_THRESH_UNDFLW = LINK_MODE[1] ? 4 : 3;
|
localparam RXBUF_THRESH_UNDFLW = LINK_MODE[1] ? 4 : 3;
|
||||||
localparam RX_EYESCAN_VS_RANGE = LINK_MODE[1] ? 2 : 0;
|
|
||||||
localparam TXPHDLY_CFG1 = LINK_MODE[1] ? 16'h000E : 16'h000F;
|
|
||||||
localparam TXPH_CFG = LINK_MODE[1] ? 16'h0723 : 16'h0323;
|
|
||||||
|
|
||||||
wire [1:0] rx_header_s;
|
wire [1:0] rx_header_s;
|
||||||
wire [127:0] rx_data_s;
|
wire [127:0] rx_data_s;
|
||||||
wire [127:0] tx_data_s;
|
wire [127:0] tx_data_s;
|
||||||
wire rx_bitslip_s;
|
wire rx_bitslip_s;
|
||||||
|
|
||||||
|
assign rx_usrclk2 = rx_clk;
|
||||||
|
assign tx_usrclk2 = tx_clk;
|
||||||
|
|
||||||
generate
|
generate
|
||||||
if (LINK_MODE[1]) begin
|
if (LINK_MODE[1]) begin
|
||||||
|
|
||||||
|
|
@ -436,12 +444,20 @@ module util_adxcvr_xch #(
|
||||||
);
|
);
|
||||||
assign tx_data_s = {64'd0, tx_data};
|
assign tx_data_s = {64'd0, tx_data};
|
||||||
|
|
||||||
|
assign rx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) ||
|
||||||
|
(XCVR_TYPE==GTHE4_TRANSCEIVERS) ? rx_clk_2x : rx_clk;
|
||||||
|
assign tx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) ||
|
||||||
|
(XCVR_TYPE==GTHE4_TRANSCEIVERS) ? tx_clk_2x : tx_clk;
|
||||||
|
|
||||||
end else begin
|
end else begin
|
||||||
|
|
||||||
assign {rx_data_open_s, rx_data} = rx_data_s;
|
assign {rx_data_open_s, rx_data} = rx_data_s;
|
||||||
assign rx_bitslip_s = 1'b0;
|
assign rx_bitslip_s = 1'b0;
|
||||||
assign tx_data_s = {96'd0, tx_data};
|
assign tx_data_s = {96'd0, tx_data};
|
||||||
|
|
||||||
|
assign rx_usrclk = rx_clk;
|
||||||
|
assign tx_usrclk = tx_clk;
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
@ -840,8 +856,8 @@ module util_adxcvr_xch #(
|
||||||
.RXSTATUS (),
|
.RXSTATUS (),
|
||||||
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
||||||
.RXUSERRDY (up_rx_user_ready),
|
.RXUSERRDY (up_rx_user_ready),
|
||||||
.RXUSRCLK (rx_clk),
|
.RXUSRCLK (rx_usrclk),
|
||||||
.RXUSRCLK2 (rx_clk),
|
.RXUSRCLK2 (rx_usrclk2),
|
||||||
.SETERRSTATUS (1'h0),
|
.SETERRSTATUS (1'h0),
|
||||||
.TSTIN (20'hfffff),
|
.TSTIN (20'hfffff),
|
||||||
.TX8B10BBYPASS (8'h0),
|
.TX8B10BBYPASS (8'h0),
|
||||||
|
|
@ -903,8 +919,8 @@ module util_adxcvr_xch #(
|
||||||
.TXSWING (1'h0),
|
.TXSWING (1'h0),
|
||||||
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
||||||
.TXUSERRDY (up_tx_user_ready),
|
.TXUSERRDY (up_tx_user_ready),
|
||||||
.TXUSRCLK (tx_clk),
|
.TXUSRCLK (tx_usrclk),
|
||||||
.TXUSRCLK2 (tx_clk));
|
.TXUSRCLK2 (tx_usrclk2));
|
||||||
// Emulate PRBS lock
|
// Emulate PRBS lock
|
||||||
assign rx_prbslocked = ~rx_prbserr_sticky;
|
assign rx_prbslocked = ~rx_prbserr_sticky;
|
||||||
end
|
end
|
||||||
|
|
@ -929,6 +945,24 @@ module util_adxcvr_xch #(
|
||||||
.DIV (3'd0),
|
.DIV (3'd0),
|
||||||
.I (tx_out_clk_s),
|
.I (tx_out_clk_s),
|
||||||
.O (tx_out_clk));
|
.O (tx_out_clk));
|
||||||
|
|
||||||
|
BUFG_GT i_rx_div2_bufg (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (1'b0),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (3'd1),
|
||||||
|
.I (rx_out_clk_s),
|
||||||
|
.O (rx_out_clk_div2));
|
||||||
|
|
||||||
|
BUFG_GT i_tx_div2_bufg (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (1'b0),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (3'd1),
|
||||||
|
.I (tx_out_clk_s),
|
||||||
|
.O (tx_out_clk_div2));
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
|
@ -950,16 +984,16 @@ module util_adxcvr_xch #(
|
||||||
.ADAPT_CFG0 (16'hf800),
|
.ADAPT_CFG0 (16'hf800),
|
||||||
.ADAPT_CFG1 (16'h0000),
|
.ADAPT_CFG1 (16'h0000),
|
||||||
.ALIGN_COMMA_DOUBLE ("FALSE"),
|
.ALIGN_COMMA_DOUBLE ("FALSE"),
|
||||||
.ALIGN_COMMA_ENABLE (10'b1111111111),
|
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
|
||||||
.ALIGN_COMMA_WORD (1),
|
.ALIGN_COMMA_WORD (1),
|
||||||
.ALIGN_MCOMMA_DET ("TRUE"),
|
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
|
||||||
.ALIGN_MCOMMA_VALUE (10'b1010000011),
|
.ALIGN_MCOMMA_VALUE (10'b1010000011),
|
||||||
.ALIGN_PCOMMA_DET ("TRUE"),
|
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
|
||||||
.ALIGN_PCOMMA_VALUE (10'b0101111100),
|
.ALIGN_PCOMMA_VALUE (10'b0101111100),
|
||||||
.A_RXOSCALRESET (1'b0),
|
.A_RXOSCALRESET (1'b0),
|
||||||
.A_RXPROGDIVRESET (1'b0),
|
.A_RXPROGDIVRESET (1'b0),
|
||||||
.A_TXPROGDIVRESET (1'b0),
|
.A_TXPROGDIVRESET (1'b0),
|
||||||
.CBCC_DATA_SOURCE_SEL ("DECODED"),
|
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
|
||||||
.CDR_SWAP_MODE_EN (1'b0),
|
.CDR_SWAP_MODE_EN (1'b0),
|
||||||
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
|
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
|
||||||
.CHAN_BOND_MAX_SKEW (1),
|
.CHAN_BOND_MAX_SKEW (1),
|
||||||
|
|
@ -1005,8 +1039,8 @@ module util_adxcvr_xch #(
|
||||||
.CPLL_REFCLK_DIV (1),
|
.CPLL_REFCLK_DIV (1),
|
||||||
.DDI_CTRL (2'b00),
|
.DDI_CTRL (2'b00),
|
||||||
.DDI_REALIGN_WAIT (15),
|
.DDI_REALIGN_WAIT (15),
|
||||||
.DEC_MCOMMA_DETECT ("TRUE"),
|
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
|
||||||
.DEC_PCOMMA_DETECT ("TRUE"),
|
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
|
||||||
.DEC_VALID_COMMA_ONLY ("FALSE"),
|
.DEC_VALID_COMMA_ONLY ("FALSE"),
|
||||||
.DFE_D_X_REL_POS (1'b0),
|
.DFE_D_X_REL_POS (1'b0),
|
||||||
.DFE_VCM_COMP_EN (1'b0),
|
.DFE_VCM_COMP_EN (1'b0),
|
||||||
|
|
@ -1039,7 +1073,7 @@ module util_adxcvr_xch #(
|
||||||
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
|
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
|
||||||
.FTS_LANE_DESKEW_CFG (4'b1111),
|
.FTS_LANE_DESKEW_CFG (4'b1111),
|
||||||
.FTS_LANE_DESKEW_EN ("FALSE"),
|
.FTS_LANE_DESKEW_EN ("FALSE"),
|
||||||
.GEARBOX_MODE (5'b00000),
|
.GEARBOX_MODE (GEARBOX_MODE),
|
||||||
.GM_BIAS_SELECT (1'b0),
|
.GM_BIAS_SELECT (1'b0),
|
||||||
.LOCAL_MASTER (1'b1),
|
.LOCAL_MASTER (1'b1),
|
||||||
.OOBDIVCTL (2'b00),
|
.OOBDIVCTL (2'b00),
|
||||||
|
|
@ -1074,14 +1108,14 @@ module util_adxcvr_xch #(
|
||||||
.RXBUF_ADDR_MODE ("FAST"),
|
.RXBUF_ADDR_MODE ("FAST"),
|
||||||
.RXBUF_EIDLE_HI_CNT (4'b1000),
|
.RXBUF_EIDLE_HI_CNT (4'b1000),
|
||||||
.RXBUF_EIDLE_LO_CNT (4'b0000),
|
.RXBUF_EIDLE_LO_CNT (4'b0000),
|
||||||
.RXBUF_EN ("TRUE"),
|
.RXBUF_EN (RXBUF_EN),
|
||||||
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
|
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
|
||||||
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
|
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
|
||||||
.RXBUF_RESET_ON_EIDLE ("FALSE"),
|
.RXBUF_RESET_ON_EIDLE ("FALSE"),
|
||||||
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
||||||
.RXBUF_THRESH_OVFLW (57),
|
.RXBUF_THRESH_OVFLW (57),
|
||||||
.RXBUF_THRESH_OVRD ("TRUE"),
|
.RXBUF_THRESH_OVRD ("TRUE"),
|
||||||
.RXBUF_THRESH_UNDFLW (3),
|
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
|
||||||
.RXCDRFREQRESET_TIME (5'b00001),
|
.RXCDRFREQRESET_TIME (5'b00001),
|
||||||
.RXCDRPHRESET_TIME (5'b00001),
|
.RXCDRPHRESET_TIME (5'b00001),
|
||||||
.RXCDR_CFG0 (16'h0000),
|
.RXCDR_CFG0 (16'h0000),
|
||||||
|
|
@ -1151,8 +1185,8 @@ module util_adxcvr_xch #(
|
||||||
.RXDLY_CFG (16'h001f),
|
.RXDLY_CFG (16'h001f),
|
||||||
.RXDLY_LCFG (16'h0030),
|
.RXDLY_LCFG (16'h0030),
|
||||||
.RXELECIDLE_CFG ("Sigcfg_4"),
|
.RXELECIDLE_CFG ("Sigcfg_4"),
|
||||||
.RXGBOX_FIFO_INIT_RD_ADDR (4),
|
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR),
|
||||||
.RXGEARBOX_EN ("FALSE"),
|
.RXGEARBOX_EN (RXGEARBOX_EN),
|
||||||
.RXISCANRESET_TIME (5'b00001),
|
.RXISCANRESET_TIME (5'b00001),
|
||||||
.RXLPM_CFG (16'h0000),
|
.RXLPM_CFG (16'h0000),
|
||||||
.RXLPM_GC_CFG (16'h1000),
|
.RXLPM_GC_CFG (16'h1000),
|
||||||
|
|
@ -1200,7 +1234,7 @@ module util_adxcvr_xch #(
|
||||||
.RX_CM_SEL (2'b11),
|
.RX_CM_SEL (2'b11),
|
||||||
.RX_CM_TRIM (4'b1010),
|
.RX_CM_TRIM (4'b1010),
|
||||||
.RX_CTLE3_LPF (8'b00000001),
|
.RX_CTLE3_LPF (8'b00000001),
|
||||||
.RX_DATA_WIDTH (40),
|
.RX_DATA_WIDTH (RX_DATA_WIDTH),
|
||||||
.RX_DDI_SEL (6'b000000),
|
.RX_DDI_SEL (6'b000000),
|
||||||
.RX_DEFER_RESET_BUF_EN ("TRUE"),
|
.RX_DEFER_RESET_BUF_EN ("TRUE"),
|
||||||
.RX_DFELPM_CFG0 (4'b0110),
|
.RX_DFELPM_CFG0 (4'b0110),
|
||||||
|
|
@ -1260,7 +1294,7 @@ module util_adxcvr_xch #(
|
||||||
.TRANS_TIME_RATE (8'h0e),
|
.TRANS_TIME_RATE (8'h0e),
|
||||||
.TST_RSV0 (8'h00),
|
.TST_RSV0 (8'h00),
|
||||||
.TST_RSV1 (8'h00),
|
.TST_RSV1 (8'h00),
|
||||||
.TXBUF_EN ("TRUE"),
|
.TXBUF_EN (TXBUF_EN),
|
||||||
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
||||||
.TXDLY_CFG (16'h0009),
|
.TXDLY_CFG (16'h0009),
|
||||||
.TXDLY_LCFG (16'h0050),
|
.TXDLY_LCFG (16'h0050),
|
||||||
|
|
@ -1268,7 +1302,7 @@ module util_adxcvr_xch #(
|
||||||
.TXDRVBIAS_P (4'b1010),
|
.TXDRVBIAS_P (4'b1010),
|
||||||
.TXFIFO_ADDR_CFG ("LOW"),
|
.TXFIFO_ADDR_CFG ("LOW"),
|
||||||
.TXGBOX_FIFO_INIT_RD_ADDR (4),
|
.TXGBOX_FIFO_INIT_RD_ADDR (4),
|
||||||
.TXGEARBOX_EN ("FALSE"),
|
.TXGEARBOX_EN (TXGEARBOX_EN),
|
||||||
.TXOUT_DIV (TX_OUT_DIV),
|
.TXOUT_DIV (TX_OUT_DIV),
|
||||||
.TXPCSRESET_TIME (5'b00011),
|
.TXPCSRESET_TIME (5'b00011),
|
||||||
.TXPHDLY_CFG0 (16'h2020),
|
.TXPHDLY_CFG0 (16'h2020),
|
||||||
|
|
@ -1294,7 +1328,7 @@ module util_adxcvr_xch #(
|
||||||
.TXSYNC_SKIP_DA (1'b0),
|
.TXSYNC_SKIP_DA (1'b0),
|
||||||
.TX_CLK25_DIV (TX_CLK25_DIV),
|
.TX_CLK25_DIV (TX_CLK25_DIV),
|
||||||
.TX_CLKMUX_EN (1'b1),
|
.TX_CLKMUX_EN (1'b1),
|
||||||
.TX_DATA_WIDTH (40),
|
.TX_DATA_WIDTH (TX_DATA_WIDTH),
|
||||||
.TX_DCD_CFG (6'b000010),
|
.TX_DCD_CFG (6'b000010),
|
||||||
.TX_DCD_EN (1'b0),
|
.TX_DCD_EN (1'b0),
|
||||||
.TX_DEEMPH0 (6'b000000),
|
.TX_DEEMPH0 (6'b000000),
|
||||||
|
|
@ -1414,7 +1448,7 @@ module util_adxcvr_xch #(
|
||||||
.RESETEXCEPTION (),
|
.RESETEXCEPTION (),
|
||||||
.RESETOVRD (1'h0),
|
.RESETOVRD (1'h0),
|
||||||
.RSTCLKENTX (1'h0),
|
.RSTCLKENTX (1'h0),
|
||||||
.RX8B10BEN (1'h1),
|
.RX8B10BEN (RX8B10BEN),
|
||||||
.RXBUFRESET (1'h0),
|
.RXBUFRESET (1'h0),
|
||||||
.RXBUFSTATUS (),
|
.RXBUFSTATUS (),
|
||||||
.RXBYTEISALIGNED (),
|
.RXBYTEISALIGNED (),
|
||||||
|
|
@ -1445,7 +1479,7 @@ module util_adxcvr_xch #(
|
||||||
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
|
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
|
||||||
.RXCTRL2 (),
|
.RXCTRL2 (),
|
||||||
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
|
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
|
||||||
.RXDATA ({rx_data_open_s, rx_data}),
|
.RXDATA (rx_data_s),
|
||||||
.RXDATAEXTENDRSVD (),
|
.RXDATAEXTENDRSVD (),
|
||||||
.RXDATAVALID (),
|
.RXDATAVALID (),
|
||||||
.RXDFEAGCCTRL (2'h1),
|
.RXDFEAGCCTRL (2'h1),
|
||||||
|
|
@ -1495,8 +1529,8 @@ module util_adxcvr_xch #(
|
||||||
.RXDLYSRESETDONE (),
|
.RXDLYSRESETDONE (),
|
||||||
.RXELECIDLE (),
|
.RXELECIDLE (),
|
||||||
.RXELECIDLEMODE (2'h3),
|
.RXELECIDLEMODE (2'h3),
|
||||||
.RXGEARBOXSLIP (1'h0),
|
.RXGEARBOXSLIP (rx_bitslip_s),
|
||||||
.RXHEADER (),
|
.RXHEADER (rx_header_s),
|
||||||
.RXHEADERVALID (),
|
.RXHEADERVALID (),
|
||||||
.RXLATCLK (1'h0),
|
.RXLATCLK (1'h0),
|
||||||
.RXLPMEN (up_rx_lpm_dfe_n),
|
.RXLPMEN (up_rx_lpm_dfe_n),
|
||||||
|
|
@ -1573,13 +1607,13 @@ module util_adxcvr_xch #(
|
||||||
.RXSYNCOUT (),
|
.RXSYNCOUT (),
|
||||||
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
||||||
.RXUSERRDY (up_rx_user_ready),
|
.RXUSERRDY (up_rx_user_ready),
|
||||||
.RXUSRCLK (rx_clk),
|
.RXUSRCLK (rx_usrclk),
|
||||||
.RXUSRCLK2 (rx_clk),
|
.RXUSRCLK2 (rx_usrclk2),
|
||||||
.RXVALID (),
|
.RXVALID (),
|
||||||
.SIGVALIDCLK (1'h0),
|
.SIGVALIDCLK (1'h0),
|
||||||
.TSTIN (20'h0),
|
.TSTIN (20'h0),
|
||||||
.TX8B10BBYPASS (8'h0),
|
.TX8B10BBYPASS (8'h0),
|
||||||
.TX8B10BEN (1'h1),
|
.TX8B10BEN (TX8B10BEN),
|
||||||
.TXBUFDIFFCTRL (3'h0),
|
.TXBUFDIFFCTRL (3'h0),
|
||||||
.TXBUFSTATUS (),
|
.TXBUFSTATUS (),
|
||||||
.TXCOMFINISH (),
|
.TXCOMFINISH (),
|
||||||
|
|
@ -1589,7 +1623,7 @@ module util_adxcvr_xch #(
|
||||||
.TXCTRL0 (16'h0),
|
.TXCTRL0 (16'h0),
|
||||||
.TXCTRL1 (16'h0),
|
.TXCTRL1 (16'h0),
|
||||||
.TXCTRL2 ({4'd0, tx_charisk}),
|
.TXCTRL2 ({4'd0, tx_charisk}),
|
||||||
.TXDATA ({96'd0, tx_data}),
|
.TXDATA (tx_data_s),
|
||||||
.TXDATAEXTENDRSVD (8'h0),
|
.TXDATAEXTENDRSVD (8'h0),
|
||||||
.TXDEEMPH (1'h0),
|
.TXDEEMPH (1'h0),
|
||||||
.TXDETECTRX (1'h0),
|
.TXDETECTRX (1'h0),
|
||||||
|
|
@ -1603,7 +1637,7 @@ module util_adxcvr_xch #(
|
||||||
.TXDLYSRESETDONE (),
|
.TXDLYSRESETDONE (),
|
||||||
.TXDLYUPDOWN (1'h0),
|
.TXDLYUPDOWN (1'h0),
|
||||||
.TXELECIDLE (1'h0),
|
.TXELECIDLE (1'h0),
|
||||||
.TXHEADER (6'h0),
|
.TXHEADER ({4'b0,tx_header}),
|
||||||
.TXINHIBIT (1'h0),
|
.TXINHIBIT (1'h0),
|
||||||
.TXLATCLK (1'h0),
|
.TXLATCLK (1'h0),
|
||||||
.TXMAINCURSOR (7'h40),
|
.TXMAINCURSOR (7'h40),
|
||||||
|
|
@ -1660,8 +1694,8 @@ module util_adxcvr_xch #(
|
||||||
.TXSYNCOUT (),
|
.TXSYNCOUT (),
|
||||||
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
||||||
.TXUSERRDY (up_tx_user_ready),
|
.TXUSERRDY (up_tx_user_ready),
|
||||||
.TXUSRCLK (tx_clk),
|
.TXUSRCLK (tx_usrclk),
|
||||||
.TXUSRCLK2 (tx_clk));
|
.TXUSRCLK2 (tx_usrclk2));
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
|
@ -1684,6 +1718,24 @@ module util_adxcvr_xch #(
|
||||||
.DIV (3'd0),
|
.DIV (3'd0),
|
||||||
.I (tx_out_clk_s),
|
.I (tx_out_clk_s),
|
||||||
.O (tx_out_clk));
|
.O (tx_out_clk));
|
||||||
|
|
||||||
|
BUFG_GT i_rx_div2_bufg (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (1'b0),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (3'd1),
|
||||||
|
.I (rx_out_clk_s),
|
||||||
|
.O (rx_out_clk_div2));
|
||||||
|
|
||||||
|
BUFG_GT i_tx_div2_bufg (
|
||||||
|
.CE (1'b1),
|
||||||
|
.CEMASK (1'b0),
|
||||||
|
.CLR (1'b0),
|
||||||
|
.CLRMASK (1'b0),
|
||||||
|
.DIV (3'd1),
|
||||||
|
.I (tx_out_clk_s),
|
||||||
|
.O (tx_out_clk_div2));
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
|
@ -1706,11 +1758,11 @@ module util_adxcvr_xch #(
|
||||||
.ADAPT_CFG1 (16'b1100100000000000),
|
.ADAPT_CFG1 (16'b1100100000000000),
|
||||||
.ADAPT_CFG2 (16'b0000000000000000),
|
.ADAPT_CFG2 (16'b0000000000000000),
|
||||||
.ALIGN_COMMA_DOUBLE ("FALSE"),
|
.ALIGN_COMMA_DOUBLE ("FALSE"),
|
||||||
.ALIGN_COMMA_ENABLE (10'b1111111111),
|
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE),
|
||||||
.ALIGN_COMMA_WORD (1),
|
.ALIGN_COMMA_WORD (1),
|
||||||
.ALIGN_MCOMMA_DET ("TRUE"),
|
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET),
|
||||||
.ALIGN_MCOMMA_VALUE (10'b1010000011),
|
.ALIGN_MCOMMA_VALUE (10'b1010000011),
|
||||||
.ALIGN_PCOMMA_DET ("TRUE"),
|
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET),
|
||||||
.ALIGN_PCOMMA_VALUE (10'b0101111100),
|
.ALIGN_PCOMMA_VALUE (10'b0101111100),
|
||||||
.A_RXOSCALRESET (1'b0),
|
.A_RXOSCALRESET (1'b0),
|
||||||
.A_RXPROGDIVRESET (1'b0),
|
.A_RXPROGDIVRESET (1'b0),
|
||||||
|
|
@ -1718,7 +1770,7 @@ module util_adxcvr_xch #(
|
||||||
.A_TXDIFFCTRL (A_TXDIFFCTRL),
|
.A_TXDIFFCTRL (A_TXDIFFCTRL),
|
||||||
.A_TXPROGDIVRESET (1'b0),
|
.A_TXPROGDIVRESET (1'b0),
|
||||||
.CAPBYPASS_FORCE (1'b0),
|
.CAPBYPASS_FORCE (1'b0),
|
||||||
.CBCC_DATA_SOURCE_SEL ("DECODED"),
|
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL),
|
||||||
.CDR_SWAP_MODE_EN (1'b0),
|
.CDR_SWAP_MODE_EN (1'b0),
|
||||||
.CFOK_PWRSVE_EN (1'b1),
|
.CFOK_PWRSVE_EN (1'b1),
|
||||||
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
|
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
|
||||||
|
|
@ -1778,8 +1830,8 @@ module util_adxcvr_xch #(
|
||||||
.CTLE3_OCAP_EXT_EN (1'b0),
|
.CTLE3_OCAP_EXT_EN (1'b0),
|
||||||
.DDI_CTRL (2'b00),
|
.DDI_CTRL (2'b00),
|
||||||
.DDI_REALIGN_WAIT (15),
|
.DDI_REALIGN_WAIT (15),
|
||||||
.DEC_MCOMMA_DETECT ("TRUE"),
|
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT),
|
||||||
.DEC_PCOMMA_DETECT ("TRUE"),
|
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT),
|
||||||
.DEC_VALID_COMMA_ONLY ("FALSE"),
|
.DEC_VALID_COMMA_ONLY ("FALSE"),
|
||||||
.DELAY_ELEC (1'b0),
|
.DELAY_ELEC (1'b0),
|
||||||
.DMONITOR_CFG0 (10'b0000000000),
|
.DMONITOR_CFG0 (10'b0000000000),
|
||||||
|
|
@ -1824,7 +1876,7 @@ module util_adxcvr_xch #(
|
||||||
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
|
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
|
||||||
.FTS_LANE_DESKEW_CFG (4'b1111),
|
.FTS_LANE_DESKEW_CFG (4'b1111),
|
||||||
.FTS_LANE_DESKEW_EN ("FALSE"),
|
.FTS_LANE_DESKEW_EN ("FALSE"),
|
||||||
.GEARBOX_MODE (5'b00000),
|
.GEARBOX_MODE (GEARBOX_MODE),
|
||||||
.ISCAN_CK_PH_SEL2 (1'b0),
|
.ISCAN_CK_PH_SEL2 (1'b0),
|
||||||
.LOCAL_MASTER (1'b1),
|
.LOCAL_MASTER (1'b1),
|
||||||
.LPBK_BIAS_CTRL (3'b100),
|
.LPBK_BIAS_CTRL (3'b100),
|
||||||
|
|
@ -1875,14 +1927,14 @@ module util_adxcvr_xch #(
|
||||||
.RXBUF_ADDR_MODE ("FAST"),
|
.RXBUF_ADDR_MODE ("FAST"),
|
||||||
.RXBUF_EIDLE_HI_CNT (4'b1000),
|
.RXBUF_EIDLE_HI_CNT (4'b1000),
|
||||||
.RXBUF_EIDLE_LO_CNT (4'b0000),
|
.RXBUF_EIDLE_LO_CNT (4'b0000),
|
||||||
.RXBUF_EN ("TRUE"),
|
.RXBUF_EN (RXBUF_EN),
|
||||||
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
|
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
|
||||||
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
|
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
|
||||||
.RXBUF_RESET_ON_EIDLE ("FALSE"),
|
.RXBUF_RESET_ON_EIDLE ("FALSE"),
|
||||||
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
||||||
.RXBUF_THRESH_OVFLW (57),
|
.RXBUF_THRESH_OVFLW (57),
|
||||||
.RXBUF_THRESH_OVRD ("TRUE"),
|
.RXBUF_THRESH_OVRD ("TRUE"),
|
||||||
.RXBUF_THRESH_UNDFLW (3),
|
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW),
|
||||||
.RXCDRFREQRESET_TIME (5'b00001),
|
.RXCDRFREQRESET_TIME (5'b00001),
|
||||||
.RXCDRPHRESET_TIME (5'b00001),
|
.RXCDRPHRESET_TIME (5'b00001),
|
||||||
.RXCDR_CFG0 (RXCDR_CFG0),
|
.RXCDR_CFG0 (RXCDR_CFG0),
|
||||||
|
|
@ -1971,8 +2023,8 @@ module util_adxcvr_xch #(
|
||||||
.RXDLY_CFG (16'b0000000000010000),
|
.RXDLY_CFG (16'b0000000000010000),
|
||||||
.RXDLY_LCFG (16'b0000000000110000),
|
.RXDLY_LCFG (16'b0000000000110000),
|
||||||
.RXELECIDLE_CFG ("SIGCFG_4"),
|
.RXELECIDLE_CFG ("SIGCFG_4"),
|
||||||
.RXGBOX_FIFO_INIT_RD_ADDR (4),
|
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR),
|
||||||
.RXGEARBOX_EN ("FALSE"),
|
.RXGEARBOX_EN (RXGEARBOX_EN),
|
||||||
.RXISCANRESET_TIME (5'b00001),
|
.RXISCANRESET_TIME (5'b00001),
|
||||||
.RXLPM_CFG (16'b0000000000000000),
|
.RXLPM_CFG (16'b0000000000000000),
|
||||||
.RXLPM_GC_CFG (16'b1000000000000000),
|
.RXLPM_GC_CFG (16'b1000000000000000),
|
||||||
|
|
@ -2019,7 +2071,7 @@ module util_adxcvr_xch #(
|
||||||
.RX_CM_SEL (3),
|
.RX_CM_SEL (3),
|
||||||
.RX_CM_TRIM (10),
|
.RX_CM_TRIM (10),
|
||||||
.RX_CTLE3_LPF (8'b11111111),
|
.RX_CTLE3_LPF (8'b11111111),
|
||||||
.RX_DATA_WIDTH (40),
|
.RX_DATA_WIDTH (RX_DATA_WIDTH),
|
||||||
.RX_DDI_SEL (6'b000000),
|
.RX_DDI_SEL (6'b000000),
|
||||||
.RX_DEFER_RESET_BUF_EN ("TRUE"),
|
.RX_DEFER_RESET_BUF_EN ("TRUE"),
|
||||||
.RX_DEGEN_CTRL (3'b011),
|
.RX_DEGEN_CTRL (3'b011),
|
||||||
|
|
@ -2086,14 +2138,14 @@ module util_adxcvr_xch #(
|
||||||
.TRANS_TIME_RATE (8'b00001110),
|
.TRANS_TIME_RATE (8'b00001110),
|
||||||
.TST_RSV0 (8'b00000000),
|
.TST_RSV0 (8'b00000000),
|
||||||
.TST_RSV1 (8'b00000000),
|
.TST_RSV1 (8'b00000000),
|
||||||
.TXBUF_EN ("TRUE"),
|
.TXBUF_EN (TXBUF_EN),
|
||||||
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
|
||||||
.TXDLY_CFG (16'b1000000000010000),
|
.TXDLY_CFG (16'b1000000000010000),
|
||||||
.TXDLY_LCFG (16'b0000000000110000),
|
.TXDLY_LCFG (16'b0000000000110000),
|
||||||
.TXDRVBIAS_N (4'b1010),
|
.TXDRVBIAS_N (4'b1010),
|
||||||
.TXFIFO_ADDR_CFG ("LOW"),
|
.TXFIFO_ADDR_CFG ("LOW"),
|
||||||
.TXGBOX_FIFO_INIT_RD_ADDR (4),
|
.TXGBOX_FIFO_INIT_RD_ADDR (4),
|
||||||
.TXGEARBOX_EN ("FALSE"),
|
.TXGEARBOX_EN (TXGEARBOX_EN),
|
||||||
.TXOUT_DIV (TX_OUT_DIV),
|
.TXOUT_DIV (TX_OUT_DIV),
|
||||||
.TXPCSRESET_TIME (5'b00011),
|
.TXPCSRESET_TIME (5'b00011),
|
||||||
.TXPHDLY_CFG0 (16'b0110000001110000),
|
.TXPHDLY_CFG0 (16'b0110000001110000),
|
||||||
|
|
@ -2123,7 +2175,7 @@ module util_adxcvr_xch #(
|
||||||
.TXSYNC_SKIP_DA (1'b0),
|
.TXSYNC_SKIP_DA (1'b0),
|
||||||
.TX_CLK25_DIV (TX_CLK25_DIV),
|
.TX_CLK25_DIV (TX_CLK25_DIV),
|
||||||
.TX_CLKMUX_EN (1'b1),
|
.TX_CLKMUX_EN (1'b1),
|
||||||
.TX_DATA_WIDTH (40),
|
.TX_DATA_WIDTH (TX_DATA_WIDTH),
|
||||||
.TX_DCC_LOOP_RST_CFG (16'b0000000000000100),
|
.TX_DCC_LOOP_RST_CFG (16'b0000000000000100),
|
||||||
.TX_DEEMPH0 (6'b000000),
|
.TX_DEEMPH0 (6'b000000),
|
||||||
.TX_DEEMPH1 (6'b000000),
|
.TX_DEEMPH1 (6'b000000),
|
||||||
|
|
@ -2284,7 +2336,7 @@ module util_adxcvr_xch #(
|
||||||
.QPLL1REFCLK (qpll1_ref_clk),
|
.QPLL1REFCLK (qpll1_ref_clk),
|
||||||
.RESETEXCEPTION (),
|
.RESETEXCEPTION (),
|
||||||
.RESETOVRD (1'd0),
|
.RESETOVRD (1'd0),
|
||||||
.RX8B10BEN (1'd1),
|
.RX8B10BEN (RX8B10BEN),
|
||||||
.RXAFECFOKEN (1'b1),
|
.RXAFECFOKEN (1'b1),
|
||||||
.RXBUFRESET (1'd0),
|
.RXBUFRESET (1'd0),
|
||||||
.RXBUFSTATUS (),
|
.RXBUFSTATUS (),
|
||||||
|
|
@ -2318,7 +2370,7 @@ module util_adxcvr_xch #(
|
||||||
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
|
.RXCTRL1 ({rx_disperr_open_s, rx_disperr}),
|
||||||
.RXCTRL2 (),
|
.RXCTRL2 (),
|
||||||
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
|
.RXCTRL3 ({rx_notintable_open_s, rx_notintable}),
|
||||||
.RXDATA ({rx_data_open_s, rx_data}),
|
.RXDATA (rx_data_s),
|
||||||
.RXDATAEXTENDRSVD (),
|
.RXDATAEXTENDRSVD (),
|
||||||
.RXDATAVALID (),
|
.RXDATAVALID (),
|
||||||
.RXDFEAGCCTRL (2'b01),
|
.RXDFEAGCCTRL (2'b01),
|
||||||
|
|
@ -2375,8 +2427,8 @@ module util_adxcvr_xch #(
|
||||||
.RXELECIDLE (),
|
.RXELECIDLE (),
|
||||||
.RXELECIDLEMODE (2'b11),
|
.RXELECIDLEMODE (2'b11),
|
||||||
.RXEQTRAINING (1'd0),
|
.RXEQTRAINING (1'd0),
|
||||||
.RXGEARBOXSLIP (1'd0),
|
.RXGEARBOXSLIP (rx_bitslip_s),
|
||||||
.RXHEADER (),
|
.RXHEADER (rx_header_s),
|
||||||
.RXHEADERVALID (),
|
.RXHEADERVALID (),
|
||||||
.RXLATCLK (1'd0),
|
.RXLATCLK (1'd0),
|
||||||
.RXLFPSTRESETDET (),
|
.RXLFPSTRESETDET (),
|
||||||
|
|
@ -2451,13 +2503,13 @@ module util_adxcvr_xch #(
|
||||||
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
||||||
.RXTERMINATION (1'd0),
|
.RXTERMINATION (1'd0),
|
||||||
.RXUSERRDY (up_rx_user_ready),
|
.RXUSERRDY (up_rx_user_ready),
|
||||||
.RXUSRCLK (rx_clk),
|
.RXUSRCLK (rx_usrclk),
|
||||||
.RXUSRCLK2 (rx_clk),
|
.RXUSRCLK2 (rx_usrclk2),
|
||||||
.RXVALID (),
|
.RXVALID (),
|
||||||
.SIGVALIDCLK (1'd0),
|
.SIGVALIDCLK (1'd0),
|
||||||
.TSTIN (20'd0),
|
.TSTIN (20'd0),
|
||||||
.TX8B10BBYPASS (8'd0),
|
.TX8B10BBYPASS (8'd0),
|
||||||
.TX8B10BEN (1'd1),
|
.TX8B10BEN (RX8B10BEN),
|
||||||
.TXBUFSTATUS (),
|
.TXBUFSTATUS (),
|
||||||
.TXCOMFINISH (),
|
.TXCOMFINISH (),
|
||||||
.TXCOMINIT (1'd0),
|
.TXCOMINIT (1'd0),
|
||||||
|
|
@ -2466,7 +2518,7 @@ module util_adxcvr_xch #(
|
||||||
.TXCTRL0 (16'd0),
|
.TXCTRL0 (16'd0),
|
||||||
.TXCTRL1 (16'd0),
|
.TXCTRL1 (16'd0),
|
||||||
.TXCTRL2 ({4'd0, tx_charisk}),
|
.TXCTRL2 ({4'd0, tx_charisk}),
|
||||||
.TXDATA ({96'd0, tx_data}),
|
.TXDATA (tx_data_s),
|
||||||
.TXDATAEXTENDRSVD (8'd0),
|
.TXDATAEXTENDRSVD (8'd0),
|
||||||
.TXDCCDONE (),
|
.TXDCCDONE (),
|
||||||
.TXDCCFORCESTART (1'd0),
|
.TXDCCFORCESTART (1'd0),
|
||||||
|
|
@ -2482,7 +2534,7 @@ module util_adxcvr_xch #(
|
||||||
.TXDLYSRESETDONE (),
|
.TXDLYSRESETDONE (),
|
||||||
.TXDLYUPDOWN (1'd0),
|
.TXDLYUPDOWN (1'd0),
|
||||||
.TXELECIDLE (1'd0),
|
.TXELECIDLE (1'd0),
|
||||||
.TXHEADER (6'd0),
|
.TXHEADER ({4'b0,tx_header}),
|
||||||
.TXINHIBIT (1'd0),
|
.TXINHIBIT (1'd0),
|
||||||
.TXLATCLK (1'd0),
|
.TXLATCLK (1'd0),
|
||||||
.TXLFPSTRESET (1'd0),
|
.TXLFPSTRESET (1'd0),
|
||||||
|
|
@ -2542,8 +2594,8 @@ module util_adxcvr_xch #(
|
||||||
.TXSYNCOUT (),
|
.TXSYNCOUT (),
|
||||||
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
||||||
.TXUSERRDY (up_tx_user_ready),
|
.TXUSERRDY (up_tx_user_ready),
|
||||||
.TXUSRCLK (tx_clk),
|
.TXUSRCLK (tx_usrclk),
|
||||||
.TXUSRCLK2 (tx_clk));
|
.TXUSRCLK2 (tx_usrclk2));
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
|
|
@ -2852,7 +2904,7 @@ module util_adxcvr_xch #(
|
||||||
.RXDLY_LCFG (16'b0000000000110000),
|
.RXDLY_LCFG (16'b0000000000110000),
|
||||||
.RXELECIDLE_CFG ("SIGCFG_4"),
|
.RXELECIDLE_CFG ("SIGCFG_4"),
|
||||||
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR),
|
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR),
|
||||||
.RXGEARBOX_EN (GEARBOX_EN),
|
.RXGEARBOX_EN (RXGEARBOX_EN),
|
||||||
.RXISCANRESET_TIME (5'b00001),
|
.RXISCANRESET_TIME (5'b00001),
|
||||||
.RXLPM_CFG (16'b0000000000000000),
|
.RXLPM_CFG (16'b0000000000000000),
|
||||||
.RXLPM_GC_CFG (16'b1111100000000000),
|
.RXLPM_GC_CFG (16'b1111100000000000),
|
||||||
|
|
@ -2914,7 +2966,7 @@ module util_adxcvr_xch #(
|
||||||
.RX_EN_SUM_RCAL_B (0),
|
.RX_EN_SUM_RCAL_B (0),
|
||||||
.RX_EYESCAN_VS_CODE (7'b0000000),
|
.RX_EYESCAN_VS_CODE (7'b0000000),
|
||||||
.RX_EYESCAN_VS_NEG_DIR (1'b0),
|
.RX_EYESCAN_VS_NEG_DIR (1'b0),
|
||||||
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE),
|
.RX_EYESCAN_VS_RANGE (2'b00),
|
||||||
.RX_EYESCAN_VS_UT_SIGN (1'b0),
|
.RX_EYESCAN_VS_UT_SIGN (1'b0),
|
||||||
.RX_FABINT_USRCLK_FLOP (1'b0),
|
.RX_FABINT_USRCLK_FLOP (1'b0),
|
||||||
.RX_I2V_FILTER_EN (1'b1),
|
.RX_I2V_FILTER_EN (1'b1),
|
||||||
|
|
@ -2974,12 +3026,12 @@ module util_adxcvr_xch #(
|
||||||
.TXFE_CFG3 (TXFE_CFG3),
|
.TXFE_CFG3 (TXFE_CFG3),
|
||||||
.TXFIFO_ADDR_CFG ("LOW"),
|
.TXFIFO_ADDR_CFG ("LOW"),
|
||||||
.TXGBOX_FIFO_INIT_RD_ADDR (4),
|
.TXGBOX_FIFO_INIT_RD_ADDR (4),
|
||||||
.TXGEARBOX_EN (GEARBOX_EN),
|
.TXGEARBOX_EN (TXGEARBOX_EN),
|
||||||
.TXOUT_DIV (TX_OUT_DIV),
|
.TXOUT_DIV (TX_OUT_DIV),
|
||||||
.TXPCSRESET_TIME (5'b00011),
|
.TXPCSRESET_TIME (5'b00011),
|
||||||
.TXPHDLY_CFG0 (16'b0110000001110000),
|
.TXPHDLY_CFG0 (16'b0110000001110000),
|
||||||
.TXPHDLY_CFG1 (TXPHDLY_CFG1),
|
.TXPHDLY_CFG1 (16'h000F),
|
||||||
.TXPH_CFG (TXPH_CFG),
|
.TXPH_CFG (16'h0323),
|
||||||
.TXPH_CFG2 (16'b0000000000000000),
|
.TXPH_CFG2 (16'b0000000000000000),
|
||||||
.TXPH_MONITOR_SEL (5'b00000),
|
.TXPH_MONITOR_SEL (5'b00000),
|
||||||
.TXPI_CFG0 (TXPI_CFG0),
|
.TXPI_CFG0 (TXPI_CFG0),
|
||||||
|
|
@ -3035,7 +3087,7 @@ module util_adxcvr_xch #(
|
||||||
.TX_PROGCLK_SEL ("PREPI"),
|
.TX_PROGCLK_SEL ("PREPI"),
|
||||||
.TX_PROGDIV_CFG (0.0),
|
.TX_PROGDIV_CFG (0.0),
|
||||||
.TX_PROGDIV_RATE (16'b0000000000000001),
|
.TX_PROGDIV_RATE (16'b0000000000000001),
|
||||||
.TX_RXDETECT_CFG (TX_RXDETECT_CFG),
|
.TX_RXDETECT_CFG (14'h032),
|
||||||
.TX_RXDETECT_REF (5),
|
.TX_RXDETECT_REF (5),
|
||||||
.TX_SAMPLE_PERIOD (3'b111),
|
.TX_SAMPLE_PERIOD (3'b111),
|
||||||
.TX_SW_MEAS (2'b00),
|
.TX_SW_MEAS (2'b00),
|
||||||
|
|
@ -3233,8 +3285,8 @@ module util_adxcvr_xch #(
|
||||||
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
.RXSYSCLKSEL (rx_sys_clk_sel_s),
|
||||||
.RXTERMINATION (1'b0),
|
.RXTERMINATION (1'b0),
|
||||||
.RXUSERRDY (up_rx_user_ready),
|
.RXUSERRDY (up_rx_user_ready),
|
||||||
.RXUSRCLK (rx_clk),
|
.RXUSRCLK (rx_usrclk),
|
||||||
.RXUSRCLK2 (rx_clk),
|
.RXUSRCLK2 (rx_usrclk2),
|
||||||
.SIGVALIDCLK (1'b0),
|
.SIGVALIDCLK (1'b0),
|
||||||
.TSTIN (20'b00000000000000000000),
|
.TSTIN (20'b00000000000000000000),
|
||||||
.TX8B10BBYPASS (8'b0),
|
.TX8B10BBYPASS (8'b0),
|
||||||
|
|
@ -3304,8 +3356,8 @@ module util_adxcvr_xch #(
|
||||||
.TXSYNCMODE (1'b0),
|
.TXSYNCMODE (1'b0),
|
||||||
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
.TXSYSCLKSEL (tx_sys_clk_sel_s),
|
||||||
.TXUSERRDY (up_tx_user_ready),
|
.TXUSERRDY (up_tx_user_ready),
|
||||||
.TXUSRCLK (tx_clk),
|
.TXUSRCLK (tx_usrclk),
|
||||||
.TXUSRCLK2 (tx_clk),
|
.TXUSRCLK2 (tx_usrclk2),
|
||||||
.BUFGTCE (),
|
.BUFGTCE (),
|
||||||
.BUFGTCEMASK (),
|
.BUFGTCEMASK (),
|
||||||
.BUFGTDIV (),
|
.BUFGTDIV (),
|
||||||
|
|
@ -3361,7 +3413,7 @@ module util_adxcvr_xch #(
|
||||||
.RXDLYSRESETDONE (),
|
.RXDLYSRESETDONE (),
|
||||||
.RXELECIDLE (),
|
.RXELECIDLE (),
|
||||||
.RXHEADER (rx_header_s),
|
.RXHEADER (rx_header_s),
|
||||||
.RXHEADERVALID (rx_headervalid_s),
|
.RXHEADERVALID (),
|
||||||
.RXLFPSTRESETDET (),
|
.RXLFPSTRESETDET (),
|
||||||
.RXLFPSU2LPEXITDET (),
|
.RXLFPSU2LPEXITDET (),
|
||||||
.RXLFPSU3WAKEDET (),
|
.RXLFPSU3WAKEDET (),
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue