kcu105/adv7511: moved hdmi/spdif out of base design
Rejeesh Kutty
parent
09b916d0c7
commit
d7993401e6
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@ -32,24 +32,16 @@ create_bd_port -dir I -from 31 -to 0 gpio1_i
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create_bd_port -dir O -from 31 -to 0 gpio1_o
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create_bd_port -dir O -from 31 -to 0 gpio1_t
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create_bd_port -dir O hdmi_out_clk
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create_bd_port -dir O hdmi_hsync
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create_bd_port -dir O hdmi_vsync
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create_bd_port -dir O hdmi_data_e
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create_bd_port -dir O -from 15 -to 0 hdmi_data
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# spdif audio
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create_bd_port -dir O spdif
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# interrupts
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create_bd_port -dir I mb_intr_05
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create_bd_port -dir I mb_intr_06
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create_bd_port -dir I mb_intr_12
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create_bd_port -dir I mb_intr_13
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create_bd_port -dir I mb_intr_14
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create_bd_port -dir I mb_intr_15
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create_bd_port -dir I -type intr mb_intr_05
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create_bd_port -dir I -type intr mb_intr_06
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create_bd_port -dir I -type intr mb_intr_07
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create_bd_port -dir I -type intr mb_intr_08
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create_bd_port -dir I -type intr mb_intr_12
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create_bd_port -dir I -type intr mb_intr_13
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create_bd_port -dir I -type intr mb_intr_14
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create_bd_port -dir I -type intr mb_intr_15
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# io settings
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@ -149,31 +141,6 @@ set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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# hdmi peripherals
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set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
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set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
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set_property -dict [list CONFIG.PCORE_DEVICE_TYPE {1}] $axi_hdmi_core
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set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma]
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set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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# audio peripherals
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set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
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set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
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set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
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set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
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set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core
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set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
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set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma]
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma
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set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma
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# connections
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ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst
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@ -225,8 +192,8 @@ ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut
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ad_connect sys_concat_intc/In4 axi_uart/interrupt
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ad_connect sys_concat_intc/In5 mb_intr_05
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ad_connect sys_concat_intc/In6 mb_intr_06
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ad_connect sys_concat_intc/In7 axi_spdif_tx_dma/mm2s_introut
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ad_connect sys_concat_intc/In8 axi_hdmi_dma/mm2s_introut
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ad_connect sys_concat_intc/In7 mb_intr_07
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ad_connect sys_concat_intc/In8 mb_intr_08
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ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt
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ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt
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@ -288,38 +255,6 @@ ad_connect gpio1_o axi_gpio/gpio2_io_o
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ad_connect gpio1_t axi_gpio/gpio2_io_t
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ad_connect sys_cpu_clk axi_spi/ext_spi_clk
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# hdmi
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ad_connect sys_200m_clk axi_hdmi_clkgen/clk
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ad_connect sys_cpu_clk axi_hdmi_clkgen/drp_clk
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ad_connect sys_cpu_clk axi_hdmi_core/m_axis_mm2s_clk
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ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
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ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
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ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
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ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
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ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync
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ad_connect axi_hdmi_core/hdmi_16_data_e hdmi_data_e
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ad_connect axi_hdmi_core/hdmi_16_data hdmi_data
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ad_connect axi_hdmi_core/m_axis_mm2s_tvalid axi_hdmi_dma/m_axis_mm2s_tvalid
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ad_connect axi_hdmi_core/m_axis_mm2s_tdata axi_hdmi_dma/m_axis_mm2s_tdata
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ad_connect axi_hdmi_core/m_axis_mm2s_tkeep axi_hdmi_dma/m_axis_mm2s_tkeep
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ad_connect axi_hdmi_core/m_axis_mm2s_tlast axi_hdmi_dma/m_axis_mm2s_tlast
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ad_connect axi_hdmi_core/m_axis_mm2s_tready axi_hdmi_dma/m_axis_mm2s_tready
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ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_dma/mm2s_fsync
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ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_core/m_axis_mm2s_fsync_ret
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# spdif audio
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ad_connect axi_spdif_tx_core/S_AXIS_TVALID axi_spdif_tx_dma/m_axis_mm2s_tvalid
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ad_connect axi_spdif_tx_core/S_AXIS_TDATA axi_spdif_tx_dma/m_axis_mm2s_tdata
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ad_connect axi_spdif_tx_core/S_AXIS_TLAST axi_spdif_tx_dma/m_axis_mm2s_tlast
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ad_connect axi_spdif_tx_core/S_AXIS_TREADY axi_spdif_tx_dma/m_axis_mm2s_tready
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ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
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ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
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ad_connect sys_cpu_clk axi_spdif_tx_core/S_AXIS_ACLK
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ad_connect sys_cpu_resetn axi_spdif_tx_core/S_AXIS_ARESETN
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ad_connect spdif axi_spdif_tx_core/spdif_tx_o
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# defaults (interconnect - processor)
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ad_cpu_interconnect 0x41400000 sys_mb_debug
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@ -331,11 +266,6 @@ ad_cpu_interconnect 0x41200000 axi_intc
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ad_cpu_interconnect 0x41600000 axi_iic_main
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ad_cpu_interconnect 0x40000000 axi_gpio
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ad_cpu_interconnect 0x44A70000 axi_spi
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ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
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ad_cpu_interconnect 0x70e00000 axi_hdmi_core
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ad_cpu_interconnect 0x43000000 axi_hdmi_dma
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ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
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ad_cpu_interconnect 0x41E00000 axi_spdif_tx_dma
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create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ddr_interconnect
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set_property CONFIG.NUM_MI {1} [get_bd_cells axi_ddr_interconnect]
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@ -354,9 +284,6 @@ ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC
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ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG
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ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S
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ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM
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ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
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ad_mem_hp0_interconnect sys_cpu_clk axi_spdif_tx_dma/M_AXI_SG
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ad_mem_hp0_interconnect sys_cpu_clk axi_spdif_tx_dma/M_AXI_MM2S
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create_bd_addr_seg -range 0x20000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \
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[get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr
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