From d79e95b77475db8b0e8e0b8cd52a628de7cc0b91 Mon Sep 17 00:00:00 2001
From: Rejeesh Kutty <rejeesh.kutty@analog.com>
Date: Wed, 12 Nov 2014 15:24:54 -0500
Subject: [PATCH] daq2: dma-fifo changes

---
 projects/daq2/common/daq2_bd.tcl | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl
index 1305180ce..a2cb0d5f9 100644
--- a/projects/daq2/common/daq2_bd.tcl
+++ b/projects/daq2/common/daq2_bd.tcl
@@ -124,11 +124,6 @@ if {$sys_zynq == 1} {
   set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
   set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
 
-if {$sys_zynq == 0} {
-
-  p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128
-}
-
 if {$sys_zynq == 1} {
 
   set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect]