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daq2: dma-fifo changes

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Rejeesh Kutty 2014-11-12 15:24:54 -05:00
parent 074662a622
commit d79e95b774
1 changed files with 0 additions and 5 deletions
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5
projects/daq2/common/daq2_bd.tcl
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@ -124,11 +124,6 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
if {$sys_zynq == 0} {
p_sys_dmafifo [current_bd_instance .] axi_ad9680_fifo 128
}
if {$sys_zynq == 1} {
set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect]