altera- sdc

library/axi_ad9144/axi_ad9144_hw.tcl

@@ -32,6 +32,7 @@ add_fileset_file axi_ad9144_channel.v VERILOG PATH axi_ad9144_channel.v
 add_fileset_file axi_ad9144_core.v    VERILOG PATH axi_ad9144_core.v
 add_fileset_file axi_ad9144_if.v      VERILOG PATH axi_ad9144_if.v
 add_fileset_file axi_ad9144.v         VERILOG PATH axi_ad9144.v TOP_LEVEL_FILE
+add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
 
 # parameters
 

library/axi_ad9680/axi_ad9680_hw.tcl

@@ -28,6 +28,7 @@ add_fileset_file axi_ad9680_pnmon.v   VERILOG PATH axi_ad9680_pnmon.v
 add_fileset_file axi_ad9680_channel.v VERILOG PATH axi_ad9680_channel.v
 add_fileset_file axi_ad9680_if.v      VERILOG PATH axi_ad9680_if.v
 add_fileset_file axi_ad9680.v         VERILOG PATH axi_ad9680.v TOP_LEVEL_FILE
+add_fileset_file ad_axi_ip_constr.sdc SDC     PATH $ad_hdl_dir/library/common/ad_axi_ip_constr.sdc
 
 # parameters
 

library/axi_dmac/axi_dmac_hw.tcl

@@ -40,6 +40,7 @@ add_fileset_file src_fifo_inf.v           VERILOG PATH src_fifo_inf.v
 add_fileset_file splitter.v               VERILOG PATH splitter.v
 add_fileset_file response_generator.v     VERILOG PATH response_generator.v
 add_fileset_file axi_dmac.v               VERILOG PATH axi_dmac.v
+add_fileset_file axi_dmac_constr.sdc      SDC     PATH axi_dmac_constr.sdc
 
 # parameters