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axi_logic_analyzer: Triggering changes on valid data

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Adrian Costina 2017-03-14 15:25:00 +02:00
parent 2a9b3cea09
commit d7edd71aef
2 changed files with 10 additions and 6 deletions
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1
library/axi_logic_analyzer/axi_logic_analyzer.v
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@ -215,6 +215,7 @@ module axi_logic_analyzer (
.reset (reset),
.data (adc_data),
.data_valid(sample_valid_la),
.trigger (trigger_m2),
.edge_detect_enable (edge_detect_enable),

15
library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
View File

@ -43,6 +43,7 @@ module axi_logic_analyzer_trigger (
input reset,
input [15:0] data,
input data_valid,
input [ 1:0] trigger,
input [17:0] edge_detect_enable,
@ -98,12 +99,14 @@ module axi_logic_analyzer_trigger (
low_level <= 'd0;
high_level <= 'd0;
end else begin
data_m1 <= {trigger, data} ;
edge_detect <= data_m1 ^ {trigger, data};
rise_edge <= (data_m1 ^ {trigger, data} ) & {trigger, data};
fall_edge <= (data_m1 ^ {trigger, data}) & ~{trigger, data};
low_level <= ~{trigger, data};
high_level <= {trigger, data};
if (data_valid == 1'b1) begin
data_m1 <= {trigger, data} ;
edge_detect <= data_m1 ^ {trigger, data};
rise_edge <= (data_m1 ^ {trigger, data} ) & {trigger, data};
fall_edge <= (data_m1 ^ {trigger, data}) & ~{trigger, data};
low_level <= ~{trigger, data};
high_level <= {trigger, data};
end
end
end