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axi_dmac: Remove second destination side register slice 

The second destination side register slice was put in place to provide
additional slack on some of the datapath control signals. It looks as if
this is no longer required for the latest version of the DMA controller.
All timing paths have sufficient margin.

So remove this extra slice register which just takes up resources and adds
pipeline latency.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-05-18 11:21:44 +02:00 committed by Lars-Peter Clausen
parent 0d337edbdf
commit d80175d895
1 changed files with 4 additions and 29 deletions
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33
library/axi_dmac/request_arb.v
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@ -756,31 +756,6 @@ axi_dmac_burst_memory #(
.dest_data_response_id(dest_data_response_id) .dest_data_response_id(dest_data_response_id)
); );
wire _dest_valid;
wire _dest_ready;
wire [DMA_DATA_WIDTH_DEST-1:0] _dest_data;
wire _dest_last;
axi_register_slice #(
.DATA_WIDTH(DMA_DATA_WIDTH_DEST + 1),
.FORWARD_REGISTERED(AXI_SLICE_DEST)
) i_dest_slice2 (
.clk(dest_clk),
.resetn(dest_resetn),
.s_axi_valid(dest_fifo_valid),
.s_axi_ready(dest_fifo_ready),
.s_axi_data({
dest_fifo_last,
dest_fifo_data
}),
.m_axi_valid(_dest_valid),
.m_axi_ready(_dest_ready),
.m_axi_data({
_dest_last,
_dest_data
})
);
axi_register_slice #( axi_register_slice #(
.DATA_WIDTH(DMA_DATA_WIDTH_DEST + 1), .DATA_WIDTH(DMA_DATA_WIDTH_DEST + 1),
.FORWARD_REGISTERED(AXI_SLICE_DEST), .FORWARD_REGISTERED(AXI_SLICE_DEST),
@ -788,11 +763,11 @@ axi_register_slice #(
) i_dest_slice ( ) i_dest_slice (
.clk(dest_clk), .clk(dest_clk),
.resetn(dest_resetn), .resetn(dest_resetn),
.s_axi_valid(_dest_valid), .s_axi_valid(dest_fifo_valid),
.s_axi_ready(_dest_ready), .s_axi_ready(dest_fifo_ready),
.s_axi_data({ .s_axi_data({
_dest_last, dest_fifo_last,
_dest_data dest_fifo_data
}), }),
.m_axi_valid(dest_valid), .m_axi_valid(dest_valid),
.m_axi_ready(dest_ready), .m_axi_ready(dest_ready),