From d802ece39e5da836be4886811e9ddebef4df2faf Mon Sep 17 00:00:00 2001
From: Istvan Csomortani <istvan.csomortani@analog.com>
Date: Mon, 1 Apr 2019 13:33:31 +0100
Subject: [PATCH] spi_engine: Reindent execution module source code

---
 .../spi_engine_execution.v                    | 294 +++++++++---------
 1 file changed, 147 insertions(+), 147 deletions(-)

diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution.v b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
index a4c8097b7..ea6f0c098 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution.v
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution.v
@@ -164,62 +164,62 @@ wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
 assign cmd_ready = idle;
 
 always @(posedge clk) begin
-        if (cmd_ready)
-                cmd_d1 <= cmd;
+  if (cmd_ready)
+   cmd_d1 <= cmd;
 end
 
 always @(posedge clk) begin
-        if (resetn == 1'b0) begin
-                active <= 1'b0;
-        end else begin
-                if (exec_cmd == 1'b1)
-                        active <= 1'b1;
-                else if (sync_ready == 1'b1 && sync_valid == 1'b1)
-                        active <= 1'b0;
-        end
+  if (resetn == 1'b0) begin
+    active <= 1'b0;
+  end else begin
+    if (exec_cmd == 1'b1)
+      active <= 1'b1;
+    else if (sync_ready == 1'b1 && sync_valid == 1'b1)
+      active <= 1'b0;
+  end
 end
 
 // Load the interface configurations from the 'Configuration Write'
 // instruction
 always @(posedge clk) begin
-        if (resetn == 1'b0) begin
-                cpha <= DEFAULT_SPI_CFG[0];
-                cpol <= DEFAULT_SPI_CFG[1];
-                three_wire <= DEFAULT_SPI_CFG[2];
-                clk_div <= DEFAULT_CLK_DIV;
-                word_length <= DATA_WIDTH;
-                left_aligned <= 8'b0;
-        end else if (exec_write_cmd == 1'b1) begin
-                 if (cmd[9:8] == REG_CONFIG) begin
-                        cpha <= cmd[0];
-                        cpol <= cmd[1];
-                        three_wire <= cmd[2];
-                end else if (cmd[9:8] == REG_CLK_DIV) begin
-                        clk_div <= cmd[7:0];
-                end else if (cmd[9:8] == REG_WORD_LENGTH) begin
-                        // the max value of this reg must be DATA_WIDTH
-                        word_length <= cmd[7:0];
-                        left_aligned <= DATA_WIDTH - cmd[7:0];
-                end
-        end
+  if (resetn == 1'b0) begin
+    cpha <= DEFAULT_SPI_CFG[0];
+    cpol <= DEFAULT_SPI_CFG[1];
+    three_wire <= DEFAULT_SPI_CFG[2];
+    clk_div <= DEFAULT_CLK_DIV;
+    word_length <= DATA_WIDTH;
+    left_aligned <= 8'b0;
+  end else if (exec_write_cmd == 1'b1) begin
+    if (cmd[9:8] == REG_CONFIG) begin
+      cpha <= cmd[0];
+      cpol <= cmd[1];
+      three_wire <= cmd[2];
+    end else if (cmd[9:8] == REG_CLK_DIV) begin
+      clk_div <= cmd[7:0];
+    end else if (cmd[9:8] == REG_WORD_LENGTH) begin
+      // the max value of this reg must be DATA_WIDTH
+      word_length <= cmd[7:0];
+      left_aligned <= DATA_WIDTH - cmd[7:0];
+    end
+  end
 end
 
 always @(posedge clk) begin
-        if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
-                clk_div_counter == 'h01) || clk_div == 'h00)
-                clk_div_last <= 1'b1;
-        else
-                clk_div_last <= 1'b0;
+  if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
+    clk_div_counter == 'h01) || clk_div == 'h00)
+    clk_div_last <= 1'b1;
+  else
+    clk_div_last <= 1'b0;
 end
 
 always @(posedge clk) begin
-        if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
-                clk_div_counter <= clk_div;
-                trigger <= 1'b1;
-        end else begin
-                clk_div_counter <= clk_div_counter - 1'b1;
-                trigger <= 1'b0;
-        end
+  if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
+    clk_div_counter <= clk_div;
+    trigger <= 1'b1;
+  end else begin
+    clk_div_counter <= clk_div_counter - 1'b1;
+    trigger <= 1'b0;
+  end
 end
 
 wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
@@ -230,84 +230,84 @@ wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last
 wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
 
 always @(posedge clk) begin
-        if (idle == 1'b1)
-                counter <= 'h00;
-        else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
-                counter <= counter + (transfer_active ? 'h1 : 'h10);
+  if (idle == 1'b1)
+    counter <= 'h00;
+  else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
+    counter <= counter + (transfer_active ? 'h1 : 'h10);
 end
 
 always @(posedge clk) begin
-        if (resetn == 1'b0) begin
-                idle <= 1'b1;
-        end else begin
-                if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
-                        idle <= 1'b0;
-                end else begin
-                        case (inst_d1)
-                        CMD_TRANSFER: begin
-                                if (transfer_active == 1'b0 && wait_for_io == 1'b0)
-                                        idle <= 1'b1;
-                        end
-                        CMD_CHIPSELECT: begin
-                                if (cs_sleep_counter_compare2)
-                                        idle <= 1'b1;
-                        end
-                        CMD_MISC: begin
-                                case (cmd_d1[8])
-                                MISC_SLEEP: begin
-                                        if (sleep_counter_compare)
-                                                idle <= 1'b1;
-                                end
-                                MISC_SYNC: begin
-                                        if (sync_ready)
-                                                idle <= 1'b1;
-                                end
-                                endcase
-                        end
-                        endcase
-                end
+  if (resetn == 1'b0) begin
+    idle <= 1'b1;
+  end else begin
+    if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
+      idle <= 1'b0;
+    end else begin
+      case (inst_d1)
+      CMD_TRANSFER: begin
+        if (transfer_active == 1'b0 && wait_for_io == 1'b0)
+          idle <= 1'b1;
+      end
+      CMD_CHIPSELECT: begin
+        if (cs_sleep_counter_compare2)
+          idle <= 1'b1;
+      end
+      CMD_MISC: begin
+        case (cmd_d1[8])
+        MISC_SLEEP: begin
+          if (sleep_counter_compare)
+            idle <= 1'b1;
         end
+        MISC_SYNC: begin
+          if (sync_ready)
+            idle <= 1'b1;
+        end
+        endcase
+      end
+      endcase
+    end
+  end
 end
 
 always @(posedge clk) begin
-        if (resetn == 1'b0) begin
-                cs <= 'hff;
-        end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
-                cs <= cmd_d1[NUM_OF_CS-1:0];
-        end
+  if (resetn == 1'b0) begin
+    cs <= 'hff;
+  end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
+    cs <= cmd_d1[NUM_OF_CS-1:0];
+  end
 end
 
 always @(posedge clk) begin
-        if (resetn == 1'b0) begin
-                sync_valid <= 1'b0;
-        end else begin
-                if (exec_sync_cmd == 1'b1) begin
-                        sync_valid <= 1'b1;
-                end else if (sync_ready == 1'b1) begin
-                        sync_valid <= 1'b0;
-                end
-        end
+  if (resetn == 1'b0) begin
+    sync_valid <= 1'b0;
+  end else begin
+    if (exec_sync_cmd == 1'b1) begin
+      sync_valid <= 1'b1;
+    end else if (sync_ready == 1'b1) begin
+      sync_valid <= 1'b0;
+    end
+  end
 end
 
 assign sync = cmd_d1[7:0];
 
 always @(posedge clk) begin
-        if (resetn == 1'b0)
-                sdo_data_ready <= 1'b0;
-        else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
-                transfer_active == 1'b1)
-                sdo_data_ready <= 1'b1;
-        else if (sdo_data_valid == 1'b1)
-                sdo_data_ready <= 1'b0;
+  if (resetn == 1'b0)
+    sdo_data_ready <= 1'b0;
+  else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
+    transfer_active == 1'b1)
+    sdo_data_ready <= 1'b1;
+  else if (sdo_data_valid == 1'b1)
+    sdo_data_ready <= 1'b0;
 end
 
 always @(posedge clk) begin
-        if (resetn == 1'b0)
-                sdi_data_valid <= 1'b0;
-        else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
-                sdi_data_valid <= 1'b1;
-        else if (sdi_data_ready == 1'b1)
-                sdi_data_valid <= 1'b0;
+  if (resetn == 1'b0)
+    sdi_data_valid <= 1'b0;
+  else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
+    sdi_data_valid <= 1'b1;
+  else if (sdi_data_ready == 1'b1)
+    sdi_data_valid <= 1'b0;
 end
 
 wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
@@ -316,57 +316,57 @@ wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
         (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
 
 always @(posedge clk) begin
-        if (idle == 1'b1) begin
-                last_transfer <= 1'b0;
-        end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
-                if (transfer_counter == cmd_d1[7:0])
-                        last_transfer <= 1'b1;
-                else
-                        last_transfer <= 1'b0;
-        end
+  if (idle == 1'b1) begin
+    last_transfer <= 1'b0;
+  end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
+    if (transfer_counter == cmd_d1[7:0])
+      last_transfer <= 1'b1;
+    else
+      last_transfer <= 1'b0;
+  end
 end
 
 always @(posedge clk) begin
-        if (resetn == 1'b0) begin
-                transfer_active <= 1'b0;
-                wait_for_io <= 1'b0;
-        end else begin
-                if (exec_transfer_cmd == 1'b1) begin
-                        wait_for_io <= 1'b1;
-                        transfer_active <= 1'b0;
-                end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
-                        wait_for_io <= 1'b0;
-                        if (last_transfer == 1'b0)
-                                transfer_active <= 1'b1;
-                        else
-                                transfer_active <= 1'b0;
-                end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
-                        if (last_transfer == 1'b1 || io_ready2 == 1'b0)
-                                transfer_active <= 1'b0;
-                        if (io_ready2 == 1'b0)
-                                wait_for_io <= 1'b1;
-                end
-        end
+  if (resetn == 1'b0) begin
+    transfer_active <= 1'b0;
+    wait_for_io <= 1'b0;
+  end else begin
+    if (exec_transfer_cmd == 1'b1) begin
+      wait_for_io <= 1'b1;
+      transfer_active <= 1'b0;
+    end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
+      wait_for_io <= 1'b0;
+      if (last_transfer == 1'b0)
+        transfer_active <= 1'b1;
+      else
+        transfer_active <= 1'b0;
+    end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
+      if (last_transfer == 1'b1 || io_ready2 == 1'b0)
+        transfer_active <= 1'b0;
+      if (io_ready2 == 1'b0)
+        wait_for_io <= 1'b1;
+    end
+  end
 end
 
 always @(posedge clk) begin
-        if (transfer_active == 1'b1 || wait_for_io == 1'b1)
-        begin
-          sdo_t <= ~sdo_enabled;
-        end else begin
-          sdo_t <= 1'b1;
-        end
+  if (transfer_active == 1'b1 || wait_for_io == 1'b1)
+  begin
+    sdo_t <= ~sdo_enabled;
+  end else begin
+    sdo_t <= 1'b1;
+  end
 end
 
 // Load the SDO parallel data into the SDO shift register. In case of a custom
 // data width, additional bit shifting must done at load.
 always @(posedge clk) begin
-        if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
-                if (first_bit == 1'b1)
-                  data_sdo_shift <= sdo_data << left_aligned;
-                else
-                  data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
-        end
+  if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
+    if (first_bit == 1'b1)
+      data_sdo_shift <= sdo_data << left_aligned;
+    else
+      data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
+  end
 end
 
 assign sdo = ((inst_d1 == CMD_TRANSFER) && (sdo_enabled)) ? data_sdo_shift[DATA_WIDTH-1] : SDO_DEFAULT;
@@ -436,11 +436,11 @@ always @(posedge clk) begin
 end
 
 always @(posedge clk) begin
-        if (transfer_active == 1'b1) begin
-          sclk <= cpol ^ cpha ^ ntx_rx;
-        end else begin
-          sclk <= cpol;
-        end
+  if (transfer_active == 1'b1) begin
+    sclk <= cpol ^ cpha ^ ntx_rx;
+  end else begin
+    sclk <= cpol;
+  end
 end
 
 endmodule