spi_engine: Reindent execution module source code
parent
6b110b6fb8
commit
d802ece39e
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@ -164,62 +164,62 @@ wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC;
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assign cmd_ready = idle;
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always @(posedge clk) begin
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if (cmd_ready)
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cmd_d1 <= cmd;
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if (cmd_ready)
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cmd_d1 <= cmd;
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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active <= 1'b0;
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end else begin
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if (exec_cmd == 1'b1)
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active <= 1'b1;
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else if (sync_ready == 1'b1 && sync_valid == 1'b1)
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active <= 1'b0;
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end
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if (resetn == 1'b0) begin
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active <= 1'b0;
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end else begin
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if (exec_cmd == 1'b1)
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active <= 1'b1;
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else if (sync_ready == 1'b1 && sync_valid == 1'b1)
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active <= 1'b0;
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end
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end
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// Load the interface configurations from the 'Configuration Write'
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// instruction
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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cpha <= DEFAULT_SPI_CFG[0];
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cpol <= DEFAULT_SPI_CFG[1];
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three_wire <= DEFAULT_SPI_CFG[2];
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clk_div <= DEFAULT_CLK_DIV;
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word_length <= DATA_WIDTH;
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left_aligned <= 8'b0;
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end else if (exec_write_cmd == 1'b1) begin
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if (cmd[9:8] == REG_CONFIG) begin
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cpha <= cmd[0];
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cpol <= cmd[1];
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three_wire <= cmd[2];
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end else if (cmd[9:8] == REG_CLK_DIV) begin
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clk_div <= cmd[7:0];
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end else if (cmd[9:8] == REG_WORD_LENGTH) begin
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// the max value of this reg must be DATA_WIDTH
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word_length <= cmd[7:0];
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left_aligned <= DATA_WIDTH - cmd[7:0];
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end
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end
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if (resetn == 1'b0) begin
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cpha <= DEFAULT_SPI_CFG[0];
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cpol <= DEFAULT_SPI_CFG[1];
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three_wire <= DEFAULT_SPI_CFG[2];
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clk_div <= DEFAULT_CLK_DIV;
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word_length <= DATA_WIDTH;
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left_aligned <= 8'b0;
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end else if (exec_write_cmd == 1'b1) begin
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if (cmd[9:8] == REG_CONFIG) begin
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cpha <= cmd[0];
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cpol <= cmd[1];
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three_wire <= cmd[2];
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end else if (cmd[9:8] == REG_CLK_DIV) begin
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clk_div <= cmd[7:0];
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end else if (cmd[9:8] == REG_WORD_LENGTH) begin
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// the max value of this reg must be DATA_WIDTH
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word_length <= cmd[7:0];
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left_aligned <= DATA_WIDTH - cmd[7:0];
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end
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end
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end
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always @(posedge clk) begin
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if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
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clk_div_counter == 'h01) || clk_div == 'h00)
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clk_div_last <= 1'b1;
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else
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clk_div_last <= 1'b0;
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if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 &&
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clk_div_counter == 'h01) || clk_div == 'h00)
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clk_div_last <= 1'b1;
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else
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clk_div_last <= 1'b0;
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end
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always @(posedge clk) begin
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if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
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clk_div_counter <= clk_div;
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trigger <= 1'b1;
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end else begin
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clk_div_counter <= clk_div_counter - 1'b1;
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trigger <= 1'b0;
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end
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if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin
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clk_div_counter <= clk_div;
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trigger <= 1'b1;
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end else begin
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clk_div_counter <= clk_div_counter - 1'b1;
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trigger <= 1'b0;
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end
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end
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wire trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0;
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@ -230,84 +230,84 @@ wire cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8] && clk_div_last
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wire cs_sleep_counter_compare2 = cs_sleep_counter2 == {cmd_d1[9:8],1'b1} && clk_div_last == 1'b1;
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always @(posedge clk) begin
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if (idle == 1'b1)
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counter <= 'h00;
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else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
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counter <= counter + (transfer_active ? 'h1 : 'h10);
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if (idle == 1'b1)
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counter <= 'h00;
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else if (clk_div_last == 1'b1 && wait_for_io == 1'b0)
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counter <= counter + (transfer_active ? 'h1 : 'h10);
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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idle <= 1'b1;
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end else begin
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if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
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idle <= 1'b0;
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end else begin
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case (inst_d1)
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CMD_TRANSFER: begin
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if (transfer_active == 1'b0 && wait_for_io == 1'b0)
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idle <= 1'b1;
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end
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CMD_CHIPSELECT: begin
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if (cs_sleep_counter_compare2)
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idle <= 1'b1;
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end
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CMD_MISC: begin
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case (cmd_d1[8])
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MISC_SLEEP: begin
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if (sleep_counter_compare)
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idle <= 1'b1;
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end
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MISC_SYNC: begin
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if (sync_ready)
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idle <= 1'b1;
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end
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endcase
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end
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endcase
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end
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if (resetn == 1'b0) begin
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idle <= 1'b1;
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end else begin
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if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin
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idle <= 1'b0;
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end else begin
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case (inst_d1)
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CMD_TRANSFER: begin
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if (transfer_active == 1'b0 && wait_for_io == 1'b0)
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idle <= 1'b1;
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end
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CMD_CHIPSELECT: begin
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if (cs_sleep_counter_compare2)
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idle <= 1'b1;
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end
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CMD_MISC: begin
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case (cmd_d1[8])
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MISC_SLEEP: begin
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if (sleep_counter_compare)
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idle <= 1'b1;
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end
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MISC_SYNC: begin
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if (sync_ready)
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idle <= 1'b1;
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end
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endcase
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end
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endcase
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end
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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cs <= 'hff;
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end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
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cs <= cmd_d1[NUM_OF_CS-1:0];
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end
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if (resetn == 1'b0) begin
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cs <= 'hff;
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end else if (inst_d1 == CMD_CHIPSELECT && cs_sleep_counter_compare == 1'b1) begin
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cs <= cmd_d1[NUM_OF_CS-1:0];
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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sync_valid <= 1'b0;
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end else begin
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if (exec_sync_cmd == 1'b1) begin
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sync_valid <= 1'b1;
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end else if (sync_ready == 1'b1) begin
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sync_valid <= 1'b0;
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end
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end
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if (resetn == 1'b0) begin
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sync_valid <= 1'b0;
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end else begin
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if (exec_sync_cmd == 1'b1) begin
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sync_valid <= 1'b1;
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end else if (sync_ready == 1'b1) begin
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sync_valid <= 1'b0;
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end
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end
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end
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assign sync = cmd_d1[7:0];
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always @(posedge clk) begin
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if (resetn == 1'b0)
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sdo_data_ready <= 1'b0;
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else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
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transfer_active == 1'b1)
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sdo_data_ready <= 1'b1;
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else if (sdo_data_valid == 1'b1)
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sdo_data_ready <= 1'b0;
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if (resetn == 1'b0)
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sdo_data_ready <= 1'b0;
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else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 &&
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transfer_active == 1'b1)
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sdo_data_ready <= 1'b1;
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else if (sdo_data_valid == 1'b1)
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sdo_data_ready <= 1'b0;
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end
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always @(posedge clk) begin
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if (resetn == 1'b0)
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sdi_data_valid <= 1'b0;
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else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
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sdi_data_valid <= 1'b1;
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else if (sdi_data_ready == 1'b1)
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sdi_data_valid <= 1'b0;
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if (resetn == 1'b0)
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sdi_data_valid <= 1'b0;
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else if (sdi_enabled == 1'b1 && last_sdi_bit == 1'b1 && trigger_rx_s == 1'b1)
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sdi_data_valid <= 1'b1;
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else if (sdi_data_ready == 1'b1)
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sdi_data_valid <= 1'b0;
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end
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wire io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) &&
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@ -316,57 +316,57 @@ wire io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) &&
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(sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1);
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always @(posedge clk) begin
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if (idle == 1'b1) begin
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last_transfer <= 1'b0;
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end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
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if (transfer_counter == cmd_d1[7:0])
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last_transfer <= 1'b1;
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else
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last_transfer <= 1'b0;
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end
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if (idle == 1'b1) begin
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last_transfer <= 1'b0;
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end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin
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if (transfer_counter == cmd_d1[7:0])
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last_transfer <= 1'b1;
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else
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last_transfer <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (resetn == 1'b0) begin
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transfer_active <= 1'b0;
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wait_for_io <= 1'b0;
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end else begin
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if (exec_transfer_cmd == 1'b1) begin
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wait_for_io <= 1'b1;
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transfer_active <= 1'b0;
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end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
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wait_for_io <= 1'b0;
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if (last_transfer == 1'b0)
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transfer_active <= 1'b1;
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else
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transfer_active <= 1'b0;
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end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
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if (last_transfer == 1'b1 || io_ready2 == 1'b0)
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transfer_active <= 1'b0;
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if (io_ready2 == 1'b0)
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wait_for_io <= 1'b1;
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end
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end
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if (resetn == 1'b0) begin
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transfer_active <= 1'b0;
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wait_for_io <= 1'b0;
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end else begin
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if (exec_transfer_cmd == 1'b1) begin
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wait_for_io <= 1'b1;
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transfer_active <= 1'b0;
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end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin
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wait_for_io <= 1'b0;
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if (last_transfer == 1'b0)
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transfer_active <= 1'b1;
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else
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transfer_active <= 1'b0;
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end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin
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if (last_transfer == 1'b1 || io_ready2 == 1'b0)
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transfer_active <= 1'b0;
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if (io_ready2 == 1'b0)
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wait_for_io <= 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (transfer_active == 1'b1 || wait_for_io == 1'b1)
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begin
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sdo_t <= ~sdo_enabled;
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end else begin
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sdo_t <= 1'b1;
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end
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if (transfer_active == 1'b1 || wait_for_io == 1'b1)
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begin
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sdo_t <= ~sdo_enabled;
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end else begin
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sdo_t <= 1'b1;
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end
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end
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// Load the SDO parallel data into the SDO shift register. In case of a custom
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// data width, additional bit shifting must done at load.
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always @(posedge clk) begin
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if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
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if (first_bit == 1'b1)
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data_sdo_shift <= sdo_data << left_aligned;
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else
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data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
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end
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if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin
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if (first_bit == 1'b1)
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data_sdo_shift <= sdo_data << left_aligned;
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else
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data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0};
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end
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end
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assign sdo = ((inst_d1 == CMD_TRANSFER) && (sdo_enabled)) ? data_sdo_shift[DATA_WIDTH-1] : SDO_DEFAULT;
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@ -436,11 +436,11 @@ always @(posedge clk) begin
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end
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always @(posedge clk) begin
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if (transfer_active == 1'b1) begin
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sclk <= cpol ^ cpha ^ ntx_rx;
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end else begin
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sclk <= cpol;
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end
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if (transfer_active == 1'b1) begin
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sclk <= cpol ^ cpha ^ ntx_rx;
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end else begin
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sclk <= cpol;
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end
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end
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endmodule
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