From d81f605ae98e459a60b0f3318247cd474a9b7448 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 14 Mar 2018 09:25:46 +0000 Subject: [PATCH] axi_ad9162: Fix code alignment, no functional changes --- library/axi_ad9162/axi_ad9162.v | 206 +++++++++++++------------- library/axi_ad9162/axi_ad9162_core.v | 214 +++++++++++++-------------- library/axi_ad9162/axi_ad9162_if.v | 93 ++++++------ 3 files changed, 242 insertions(+), 271 deletions(-) diff --git a/library/axi_ad9162/axi_ad9162.v b/library/axi_ad9162/axi_ad9162.v index 0b17d1fa0..ce60e961c 100644 --- a/library/axi_ad9162/axi_ad9162.v +++ b/library/axi_ad9162/axi_ad9162.v @@ -40,25 +40,25 @@ module axi_ad9162 #( parameter ID = 0, parameter DAC_DATAPATH_DISABLE = 0) ( - // jesd interface - // tx_clk is (line-rate/40) - + // jesd interface + // tx_clk is (line-rate/40) + input tx_clk, output tx_valid, output [255:0] tx_data, input tx_ready, - - // dma interface - + + // dma interface + output dac_clk, output dac_valid, output dac_enable, input [255:0] dac_ddata, input dac_dovf, input dac_dunf, - - // axi interface - + + // axi interface + input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, @@ -80,106 +80,98 @@ module axi_ad9162 #( output [ 31:0] s_axi_rdata, output [ 1:0] s_axi_rresp, input s_axi_rready); - - - - - - - - - - // internal clocks and resets - - wire dac_rst; - wire up_clk; - wire up_rstn; - - // internal signals - - wire [255:0] dac_data_s; - wire up_wreq_s; - wire [ 13:0] up_waddr_s; - wire [ 31:0] up_wdata_s; - wire up_wack_s; - wire up_rreq_s; - wire [ 13:0] up_raddr_s; - wire [ 31:0] up_rdata_s; - wire up_rack_s; - - // signal name changes - - assign up_clk = s_axi_aclk; - assign up_rstn = s_axi_aresetn; - // defaults + // internal clocks and resets - assign tx_valid = 1'b1; - - // device interface - - axi_ad9162_if i_if ( - .tx_clk (tx_clk), - .tx_data (tx_data), - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_data (dac_data_s)); - - // core - - axi_ad9162_core #( - .ID (ID), - .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) - i_core ( - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_data (dac_data_s), - .dac_valid (dac_valid), - .dac_enable (dac_enable), - .dac_ddata (dac_ddata), - .dac_dovf (dac_dovf), - .dac_dunf (dac_dunf), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); - - // up bus interface - - up_axi i_up_axi ( - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_axi_awvalid (s_axi_awvalid), - .up_axi_awaddr (s_axi_awaddr), - .up_axi_awready (s_axi_awready), - .up_axi_wvalid (s_axi_wvalid), - .up_axi_wdata (s_axi_wdata), - .up_axi_wstrb (s_axi_wstrb), - .up_axi_wready (s_axi_wready), - .up_axi_bvalid (s_axi_bvalid), - .up_axi_bresp (s_axi_bresp), - .up_axi_bready (s_axi_bready), - .up_axi_arvalid (s_axi_arvalid), - .up_axi_araddr (s_axi_araddr), - .up_axi_arready (s_axi_arready), - .up_axi_rvalid (s_axi_rvalid), - .up_axi_rresp (s_axi_rresp), - .up_axi_rdata (s_axi_rdata), - .up_axi_rready (s_axi_rready), - .up_wreq (up_wreq_s), - .up_waddr (up_waddr_s), - .up_wdata (up_wdata_s), - .up_wack (up_wack_s), - .up_rreq (up_rreq_s), - .up_raddr (up_raddr_s), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); + wire dac_rst; + wire up_clk; + wire up_rstn; + + // internal signals + + wire [255:0] dac_data_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // defaults + + assign tx_valid = 1'b1; + + // device interface + + axi_ad9162_if i_if ( + .tx_clk (tx_clk), + .tx_data (tx_data), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data (dac_data_s)); + + // core + + axi_ad9162_core #( + .ID (ID), + .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)) + i_core ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data (dac_data_s), + .dac_valid (dac_valid), + .dac_enable (dac_enable), + .dac_ddata (dac_ddata), + .dac_dovf (dac_dovf), + .dac_dunf (dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); endmodule diff --git a/library/axi_ad9162/axi_ad9162_core.v b/library/axi_ad9162/axi_ad9162_core.v index 7177b95f5..c201af770 100644 --- a/library/axi_ad9162/axi_ad9162_core.v +++ b/library/axi_ad9162/axi_ad9162_core.v @@ -40,22 +40,22 @@ module axi_ad9162_core #( parameter ID = 0, parameter DATAPATH_DISABLE = 0) ( - // dac interface - + // dac interface + input dac_clk, output dac_rst, output [255:0] dac_data, - - // dma interface - + + // dma interface + output dac_valid, output dac_enable, input [255:0] dac_ddata, input dac_dovf, input dac_dunf, - - // processor interface - + + // processor interface + input up_rstn, input up_clk, input up_wreq, @@ -66,112 +66,100 @@ module axi_ad9162_core #( input [ 13:0] up_raddr, output reg [ 31:0] up_rdata, output reg up_rack); - - - - - - - - - - - // internal registers - - - // internal signals - - wire dac_sync_s; - wire dac_datafmt_s; - wire [ 31:0] up_rdata_0_s; - wire up_rack_0_s; - wire up_wack_0_s; - wire [ 31:0] up_rdata_s; - wire up_rack_s; - wire up_wack_s; - - // dac valid - - assign dac_valid = 1'b1; - - // processor read interface - - always @(negedge up_rstn or posedge up_clk) begin - if (up_rstn == 0) begin - up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; - end else begin - up_rdata <= up_rdata_s | up_rdata_0_s; - up_rack <= up_rack_s | up_rack_0_s; - up_wack <= up_wack_s | up_wack_0_s; - end + + // internal signals + + wire dac_sync_s; + wire dac_datafmt_s; + wire [ 31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + // dac valid + + assign dac_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s; + up_rack <= up_rack_s | up_rack_0_s; + up_wack <= up_wack_s | up_wack_0_s; end - - // dac channel - - axi_ad9162_channel #( - .CHANNEL_ID (0), - .DATAPATH_DISABLE (DATAPATH_DISABLE)) - i_channel_0 ( - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_enable (dac_enable), - .dac_data (dac_data), - .dma_data (dac_ddata), - .dac_data_sync (dac_sync_s), - .dac_dds_format (dac_datafmt_s), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack_0_s), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata_0_s), - .up_rack (up_rack_0_s)); - - // dac common processor interface - - up_dac_common #(.ID(ID)) i_up_dac_common ( - .mmcm_rst (), - .dac_clk (dac_clk), - .dac_rst (dac_rst), - .dac_sync (dac_sync_s), - .dac_frame (), - .dac_clksel (), - .dac_par_type (), - .dac_par_enb (), - .dac_r1_mode (), - .dac_datafmt (dac_datafmt_s), - .dac_datarate (), - .dac_status (1'b1), - .dac_status_ovf (dac_dovf), - .dac_status_unf (dac_dunf), - .dac_clk_ratio (32'd16), - .up_dac_ce (), - .up_drp_sel (), - .up_drp_wr (), - .up_drp_addr (), - .up_drp_wdata (), - .up_drp_rdata (32'd0), - .up_drp_ready (1'd0), - .up_drp_locked (1'd1), - .up_usr_chanmax (), - .dac_usr_chanmax (8'd0), - .up_dac_gpio_in (32'd0), - .up_dac_gpio_out (), - .up_rstn (up_rstn), - .up_clk (up_clk), - .up_wreq (up_wreq), - .up_waddr (up_waddr), - .up_wdata (up_wdata), - .up_wack (up_wack_s), - .up_rreq (up_rreq), - .up_raddr (up_raddr), - .up_rdata (up_rdata_s), - .up_rack (up_rack_s)); + end + + // dac channel + + axi_ad9162_channel #( + .CHANNEL_ID (0), + .DATAPATH_DISABLE (DATAPATH_DISABLE)) + i_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable), + .dac_data (dac_data), + .dma_data (dac_ddata), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_0_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_0_s), + .up_rack (up_rack_0_s)); + + // dac common processor interface + + up_dac_common #(.ID(ID)) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_s), + .dac_frame (), + .dac_clksel (), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datarate (), + .dac_status (1'b1), + .dac_status_ovf (dac_dovf), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd16), + .up_dac_ce (), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd0), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); endmodule diff --git a/library/axi_ad9162/axi_ad9162_if.v b/library/axi_ad9162/axi_ad9162_if.v index 96559baa7..5178570c3 100644 --- a/library/axi_ad9162/axi_ad9162_if.v +++ b/library/axi_ad9162/axi_ad9162_if.v @@ -37,66 +37,57 @@ module axi_ad9162_if ( - // jesd interface - // tx_clk is (line-rate/40) - + // jesd interface + // tx_clk is (line-rate/40) + input tx_clk, output reg [255:0] tx_data, - - // dac interface - + + // dac interface + output dac_clk, input dac_rst, input [255:0] dac_data); - + // reorder data for the jesd links - - - + assign dac_clk = tx_clk; - // internal registers + always @(posedge tx_clk) begin + tx_data[255:248] <= dac_data[247:240]; + tx_data[247:240] <= dac_data[183:176]; + tx_data[239:232] <= dac_data[119:112]; + tx_data[231:224] <= dac_data[ 55: 48]; + tx_data[223:216] <= dac_data[255:248]; + tx_data[215:208] <= dac_data[191:184]; + tx_data[207:200] <= dac_data[127:120]; + tx_data[199:192] <= dac_data[ 63: 56]; + tx_data[191:184] <= dac_data[231:224]; + tx_data[183:176] <= dac_data[167:160]; + tx_data[175:168] <= dac_data[103: 96]; + tx_data[167:160] <= dac_data[ 39: 32]; + tx_data[159:152] <= dac_data[239:232]; + tx_data[151:144] <= dac_data[175:168]; + tx_data[143:136] <= dac_data[111:104]; + tx_data[135:128] <= dac_data[ 47: 40]; + tx_data[127:120] <= dac_data[215:208]; + tx_data[119:112] <= dac_data[151:144]; + tx_data[111:104] <= dac_data[ 87: 80]; + tx_data[103: 96] <= dac_data[ 23: 16]; + tx_data[ 95: 88] <= dac_data[223:216]; + tx_data[ 87: 80] <= dac_data[159:152]; + tx_data[ 79: 72] <= dac_data[ 95: 88]; + tx_data[ 71: 64] <= dac_data[ 31: 24]; + tx_data[ 63: 56] <= dac_data[199:192]; + tx_data[ 55: 48] <= dac_data[135:128]; + tx_data[ 47: 40] <= dac_data[ 71: 64]; + tx_data[ 39: 32] <= dac_data[ 7: 0]; + tx_data[ 31: 24] <= dac_data[207:200]; + tx_data[ 23: 16] <= dac_data[143:136]; + tx_data[ 15: 8] <= dac_data[ 79: 72]; + tx_data[ 7: 0] <= dac_data[ 15: 8]; + end - - // reorder data for the jesd links - - assign dac_clk = tx_clk; - - always @(posedge tx_clk) begin - tx_data[255:248] <= dac_data[247:240]; - tx_data[247:240] <= dac_data[183:176]; - tx_data[239:232] <= dac_data[119:112]; - tx_data[231:224] <= dac_data[ 55: 48]; - tx_data[223:216] <= dac_data[255:248]; - tx_data[215:208] <= dac_data[191:184]; - tx_data[207:200] <= dac_data[127:120]; - tx_data[199:192] <= dac_data[ 63: 56]; - tx_data[191:184] <= dac_data[231:224]; - tx_data[183:176] <= dac_data[167:160]; - tx_data[175:168] <= dac_data[103: 96]; - tx_data[167:160] <= dac_data[ 39: 32]; - tx_data[159:152] <= dac_data[239:232]; - tx_data[151:144] <= dac_data[175:168]; - tx_data[143:136] <= dac_data[111:104]; - tx_data[135:128] <= dac_data[ 47: 40]; - tx_data[127:120] <= dac_data[215:208]; - tx_data[119:112] <= dac_data[151:144]; - tx_data[111:104] <= dac_data[ 87: 80]; - tx_data[103: 96] <= dac_data[ 23: 16]; - tx_data[ 95: 88] <= dac_data[223:216]; - tx_data[ 87: 80] <= dac_data[159:152]; - tx_data[ 79: 72] <= dac_data[ 95: 88]; - tx_data[ 71: 64] <= dac_data[ 31: 24]; - tx_data[ 63: 56] <= dac_data[199:192]; - tx_data[ 55: 48] <= dac_data[135:128]; - tx_data[ 47: 40] <= dac_data[ 71: 64]; - tx_data[ 39: 32] <= dac_data[ 7: 0]; - tx_data[ 31: 24] <= dac_data[207:200]; - tx_data[ 23: 16] <= dac_data[143:136]; - tx_data[ 15: 8] <= dac_data[ 79: 72]; - tx_data[ 7: 0] <= dac_data[ 15: 8]; - end - endmodule // ***************************************************************************