axi_ad9162: Fix code alignment, no functional changes

library/axi_ad9162/axi_ad9162.v

@@ -81,14 +81,6 @@ module axi_ad9162 #(
   output      [ 1:0]      s_axi_rresp,
   input                   s_axi_rready);
 
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   // internal clocks and resets
 
   wire              dac_rst;

library/axi_ad9162/axi_ad9162_core.v

@@ -67,18 +67,6 @@ module axi_ad9162_core #(
   output  reg [ 31:0]     up_rdata,
   output  reg             up_rack);
 
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-    // internal registers
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   // internal signals
 
   wire                    dac_sync_s;

library/axi_ad9162/axi_ad9162_if.v

@@ -49,15 +49,6 @@ module axi_ad9162_if (
   input                   dac_rst,
   input       [255:0]     dac_data);
 
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-    // internal registers
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   // reorder data for the jesd links
 
   assign dac_clk = tx_clk;