library/common- altera variations

library/common/ad_cmos_clk.v

@@ -39,6 +39,9 @@
 
 module ad_cmos_clk (
 
+  rst,
+  locked,
+
   clk_in,
   clk);
 
@@ -46,6 +49,9 @@ module ad_cmos_clk (
   localparam  SERIES7       = 0;
   localparam  VIRTEX6       = 1;
 
+  input     rst;
+  output    locked;
+
   input     clk_in;
   output    clk;
 
@@ -53,6 +59,10 @@ module ad_cmos_clk (
 
   wire      clk_ibuf_s;
 
+  // defaults
+
+  assign locked = 1'b1;
+
   // instantiations
 
   IBUFG i_rx_clk_ibuf (

library/common/ad_lvds_clk.v

@@ -41,6 +41,9 @@
 
 module ad_lvds_clk (
 
+  rst,
+  locked,
+
   clk_in_p,
   clk_in_n,
   clk);
@@ -49,6 +52,9 @@ module ad_lvds_clk (
   localparam  SERIES7       = 0;
   localparam  VIRTEX6       = 1;
 
+  input     rst;
+  output    locked;
+
   input     clk_in_p;
   input     clk_in_n;
   output    clk;
@@ -57,6 +63,10 @@ module ad_lvds_clk (
 
   wire      clk_ibuf_s;
 
+  // defaults
+
+  assign locked <= 1'b1;
+
   // instantiations
 
   IBUFGDS i_rx_clk_ibuf (

library/common/altera/ad_cmos_clk.v

@@ -39,6 +39,9 @@
 
 module ad_cmos_clk (
 
+  rst,
+  locked,
+
   clk_in,
   clk);
 
@@ -46,16 +49,19 @@ module ad_cmos_clk (
   localparam  SERIES7       = 0;
   localparam  VIRTEX6       = 1;
 
+  input     rst;
+  output    locked;
+
   input     clk_in;
   output    clk;
 
   // instantiations
 
   alt_clk i_clk (
-    .rst (1'b0),
+    .rst (rst),
     .refclk (clk_in),
     .outclk_0 (clk),
-    .locked ());
+    .locked (locked));
 
 endmodule
 

library/common/altera/ad_cmos_in.v

@@ -93,7 +93,7 @@ module ad_cmos_in (
 
   // instantiations
 
-  alt_cmos_in i_rx_data_iddr (
+  alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in),
     .dout ({rx_data_p, rx_data_n}));

library/common/altera/ad_cmos_out.v

@@ -94,7 +94,7 @@ module ad_cmos_out (
 
   // instantiations
 
-  alt_cmos_out i_tx_data_oddr (
+  alt_ddio_out i_tx_data_oddr (
     .ck (tx_clk),
     .din ({tx_data_p, tx_data_n}),
     .pad_out (tx_data_out));

library/common/altera/ad_lvds_clk.v

@@ -39,12 +39,18 @@
 
 module ad_lvds_clk (
 
+  rst,
+  locked,
+
   clk_in_p,
   clk_in_n,
   clk);
 
   parameter   DEVICE_TYPE       = 0;
 
+  input     rst;
+  output    locked;
+
   input     clk_in_p;
   input     clk_in_n;
   output    clk;
@@ -52,10 +58,10 @@ module ad_lvds_clk (
   // instantiations
 
   alt_clk i_clk (
-    .rst (1'b0),
+    .rst (rst),
     .refclk (clk_in_p),
     .outclk_0 (clk),
-    .locked ());
+    .locked (locked));
 
 endmodule
 

library/common/altera/ad_lvds_in.v

@@ -95,10 +95,9 @@ module ad_lvds_in (
 
   // instantiations
 
-  alt_lvds_in i_rx_data_iddr (
+  alt_ddio_in i_rx_data_iddr (
     .ck (rx_clk),
     .pad_in (rx_data_in_p),
-    .pad_in_b (rx_data_in_n),
     .dout ({rx_data_p, rx_data_n}));
 
 endmodule

library/common/altera/ad_lvds_out.v

@@ -96,11 +96,10 @@ module ad_lvds_out (
 
   // instantiations
 
-  alt_lvds_out i_tx_data_oddr (
+  alt_ddio_out i_tx_data_oddr (
     .ck (tx_clk),
     .din ({tx_data_p, tx_data_n}),
-    .pad_out (tx_data_out_p),
+    .pad_out (tx_data_out_p));
-    .pad_out_b (tx_data_out_n));
 
 endmodule