From d82f61b9af75392b151cba09bb5b6287e65a8017 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 21 Dec 2020 10:10:32 +0000 Subject: [PATCH] util_axis_fifo: Add KEEP synthesis attribute for zerodeep CDC Vivado synthesis is optimizing out the zerodeep block, resulting untreated clock domain crossing. Set KEEP attribute for the registers. --- library/util_axis_fifo/util_axis_fifo.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/util_axis_fifo/util_axis_fifo.v b/library/util_axis_fifo/util_axis_fifo.v index efe28cc1e..2dc54009d 100644 --- a/library/util_axis_fifo/util_axis_fifo.v +++ b/library/util_axis_fifo/util_axis_fifo.v @@ -61,7 +61,7 @@ generate if (ADDRESS_WIDTH == 0) begin : zerodeep /* it's not a real FIFO, just if (ASYNC_CLK) begin - reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; + (* KEEP = "yes" *) reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; reg s_axis_waddr = 1'b0; reg m_axis_raddr = 1'b0;