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util_axis_fifo: Add KEEP synthesis attribute for zerodeep CDC 

Vivado synthesis is optimizing out the zerodeep block, resulting untreated
clock domain crossing. Set KEEP attribute for the registers.
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Istvan Csomortani 2020-12-21 10:10:32 +00:00 committed by István Csomortáni
parent 235fb4859a
commit d82f61b9af
1 changed files with 1 additions and 1 deletions
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2
library/util_axis_fifo/util_axis_fifo.v
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@ -61,7 +61,7 @@ generate if (ADDRESS_WIDTH == 0) begin : zerodeep /* it's not a real FIFO, just
if (ASYNC_CLK) begin if (ASYNC_CLK) begin
reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; (* KEEP = "yes" *) reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
reg s_axis_waddr = 1'b0; reg s_axis_waddr = 1'b0;
reg m_axis_raddr = 1'b0; reg m_axis_raddr = 1'b0;