zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

util_clkdiv: Register output port as a clock (#33) 

If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.

Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
main
Matthew Fornero 2017-06-19 02:40:53 -04:00 committed by Istvan Csomortani
parent dc94dd3ea7
commit d840baee28
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
library/util_clkdiv/util_clkdiv_ip.tcl
View File

@ -22,4 +22,7 @@ set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters S
set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \
[list {"clk_out" "CLK"}]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]