From d844167850119df3ddab854472ad7f15fc7940fe Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 18 Nov 2019 11:04:47 +0200 Subject: [PATCH] axi_adc_trigger: Fix trigger jitter A trigger jitter was added by fix on the external trigger input. It manifests at input sampling frequencies lower than the maximum frequency. Added the required reset and CE(valid) signal to the last output stages of the trigger to obtain the desired functionality for all sampling rates. --- library/axi_adc_trigger/axi_adc_trigger.v | 34 +++++++++++++++-------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/library/axi_adc_trigger/axi_adc_trigger.v b/library/axi_adc_trigger/axi_adc_trigger.v index 7e850c0da..1ee8e3e6b 100644 --- a/library/axi_adc_trigger/axi_adc_trigger.v +++ b/library/axi_adc_trigger/axi_adc_trigger.v @@ -278,23 +278,35 @@ module axi_adc_trigger #( end - // keep data in sync with the trigger. The trigger bypasses the variable fifo. - // The data goes through and it is delayed with 4 clock cycles) + // 1. keep data in sync with the trigger. The trigger bypasses the variable + // fifo. The data goes through and it is delayed with 4 clock cycles) + // 2. For non max sample rate of the ADC, the trigger signal that originates + // from an external source is stored until the valid acknowledges the trigger. always @(posedge clk) begin - trigger_out_m1 <= trigger_out_s; - trigger_out_m2 <= trigger_out_m1; - if (trigger_out_m1 & ~trigger_out_s) begin - trigger_out_hold <= 1'b1; - end - if (trigger_out_ack) begin + if (reset == 1'b1) begin + trigger_out_m1 <= 1'b0; + trigger_out_m2 <= 1'b0; + trigger_out_ack <= 1'b0; trigger_out_hold <= 1'b0; + end else begin + if (data_out_valid == 1'b1) begin + trigger_out_m1 <= trigger_out_s | trigger_out_hold; + trigger_out_m2 <= trigger_out_m1; + trigger_out_ack <= trigger_out_hold; + end + if (~trigger_out_m1 & trigger_out_s & ~data_out_valid) begin + trigger_out_hold <= 1'b1; + end + if (trigger_out_ack) begin + trigger_out_hold <= 1'b0; + end end - - trigger_out_ack <= trigger_out_hold & (data_valid_a | data_valid_b); end + assign data_out_valid = data_valid_a | data_valid_b; + assign trigger_out_la = trigger_out_mixed; - assign trigger_out = trigger_out_hold | trigger_out_m2; + assign trigger_out = trigger_out_m2; always @(posedge clk) begin data_a_trig <= (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]};