From d8e11cfce5674a3e58c830b0ef5e6da8ad686c22 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 20 Nov 2018 14:00:55 +0000 Subject: [PATCH] daq2/3: update DAC TPL base addresses The TPL for DACs can be relocated to addresses which match the software expectations. --- projects/daq2/common/daq2_bd.tcl | 2 +- projects/daq2/common/daq2_qsys.tcl | 2 +- projects/daq3/common/daq3_bd.tcl | 2 +- projects/daq3/common/daq3_qsys.tcl | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 3e840b45e..7c5e01fb9 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -157,7 +157,7 @@ ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req # interconnect (cpu) ad_cpu_interconnect 0x44A60000 axi_ad9144_xcvr -ad_cpu_interconnect 0x44A00000 axi_ad9144_core +ad_cpu_interconnect 0x44A04000 axi_ad9144_core ad_cpu_interconnect 0x44A90000 axi_ad9144_jesd ad_cpu_interconnect 0x7c420000 axi_ad9144_dma ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr diff --git a/projects/daq2/common/daq2_qsys.tcl b/projects/daq2/common/daq2_qsys.tcl index c1f961e50..9d91b73d6 100644 --- a/projects/daq2/common/daq2_qsys.tcl +++ b/projects/daq2/common/daq2_qsys.tcl @@ -184,7 +184,7 @@ ad_cpu_interconnect 0x00029000 avl_adxcfg_1.rcfg_s0 ad_cpu_interconnect 0x0002a000 avl_adxcfg_2.rcfg_s0 ad_cpu_interconnect 0x0002b000 avl_adxcfg_3.rcfg_s0 ad_cpu_interconnect 0x0002c000 axi_ad9144_dma.s_axi -ad_cpu_interconnect 0x00030000 axi_ad9144_core.s_axi +ad_cpu_interconnect 0x00034000 axi_ad9144_core.s_axi ad_cpu_interconnect 0x00040000 ad9680_jesd204.link_reconfig ad_cpu_interconnect 0x00044000 ad9680_jesd204.link_management diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index dd0c09f0c..1119aed43 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -156,7 +156,7 @@ for {set i 0} {$i < 2} {incr i} { # interconnect (cpu) ad_cpu_interconnect 0x44A60000 axi_ad9152_xcvr -ad_cpu_interconnect 0x44A00000 axi_ad9152_core +ad_cpu_interconnect 0x44A04000 axi_ad9152_core ad_cpu_interconnect 0x44A90000 axi_ad9152_jesd ad_cpu_interconnect 0x7c420000 axi_ad9152_dma ad_cpu_interconnect 0x44A50000 axi_ad9680_xcvr diff --git a/projects/daq3/common/daq3_qsys.tcl b/projects/daq3/common/daq3_qsys.tcl index 433583143..ab562637c 100644 --- a/projects/daq3/common/daq3_qsys.tcl +++ b/projects/daq3/common/daq3_qsys.tcl @@ -177,7 +177,7 @@ ad_cpu_interconnect 0x00429000 avl_adxcfg_1.rcfg_s0 ad_cpu_interconnect 0x0042a000 avl_adxcfg_2.rcfg_s0 ad_cpu_interconnect 0x0042b000 avl_adxcfg_3.rcfg_s0 ad_cpu_interconnect 0x0042c000 axi_ad9152_dma.s_axi -ad_cpu_interconnect 0x00430000 axi_ad9152_core.s_axi +ad_cpu_interconnect 0x00434000 axi_ad9152_core.s_axi ad_cpu_interconnect 0x00440000 ad9680_jesd204.link_reconfig ad_cpu_interconnect 0x00444000 ad9680_jesd204.link_management