fmcomms11: Connect DAC fifo bypass to a GPIO

GPIO[60] can be used to control the bypass line of the
util_dacfifo module.
main
Istvan Csomortani 2019-05-29 13:53:32 +03:00 committed by István Csomortáni
parent 70b7d69ff8
commit d9230fdc5e
2 changed files with 7 additions and 5 deletions

View File

@ -28,6 +28,10 @@ set dac_fifo_address_width 10
set dac_data_width 256
set dac_dma_data_width 256
# DAC FIFO bypass
create_bd_port -dir I dac_fifo_bypass
# dac peripherals
ad_ip_instance axi_adxcvr axi_ad9162_xcvr
@ -141,6 +145,7 @@ ad_connect axi_ad9162_fifo/dma_ready axi_ad9162_dma/m_axis_ready
ad_connect axi_ad9162_fifo/dma_data axi_ad9162_dma/m_axis_data
ad_connect axi_ad9162_fifo/dma_valid axi_ad9162_dma/m_axis_valid
ad_connect axi_ad9162_fifo/dma_xfer_last axi_ad9162_dma/m_axis_last
ad_connect dac_fifo_bypass axi_ad9162_fifo/bypass
# connections (adc)
@ -194,7 +199,3 @@ ad_cpu_interrupt ps-11 mb-14 axi_ad9625_jesd/irq
ad_cpu_interrupt ps-12 mb-12 axi_ad9162_dma/irq
ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
# unused
ad_connect axi_ad9162_fifo/bypass GND

View File

@ -306,7 +306,8 @@ module system_top (
.tx_data_7_p (tx_data_p[7]),
.tx_ref_clk_0 (trx_ref_clk),
.tx_sync_0 (tx_sync),
.tx_sysref_0 (1'b0));
.tx_sysref_0 (1'b0),
.dac_fifo_bypass (gpio_o[60]));
endmodule