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ad7616_sdz: Use SPI Engine for serial mode 

This commit makes the following changes:
Add SPI Engine for serial mode
Add SER_PAR_N build parameter, set default 1 for serial
Fix irq consistency in ad7616_bd.tcl
Fix regmap and offload names
Fix system_top.v GPIOs
main
Stanca Pop 2022-03-16 13:27:38 +02:00 committed by StancaPop
parent 9ba84cf7c0
commit d97550fa71
15 changed files with 236 additions and 125 deletions
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155
projects/ad7616_sdz/common/ad7616_bd.tcl
View File

@ -2,87 +2,162 @@
## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
##--------------------------------------------------------------
# system level parameters
set SI_OR_PI $ad_project_params(SI_OR_PI)
# IMPORTANT: Set AD7616 operation and interface mode
#
# The get_env_param procedure retrieves parameter value from the environment if exists,
# other case returns the default value specified in its second parameter field.
#
# How to use over-writable parameters from the environment:
#
# e.g.
# make SER_PAR_N=0
#
# SER_PAR_N - Defines the interface type (serial OR parallel)
# - Default value is 1
#
# LEGEND: Serial - 1
# Parallel - 0
#
# NOTE : This switch is a 'hardware' switch. Please rebuild the design if the
# variable has been changed.
# SL5 - mounted - Serial
# SL5 - unmounted - Parallel
#
##--------------------------------------------------------------
puts "build parameters: SI_OR_PI: $SI_OR_PI"
# data interfaces
create_bd_port -dir O rx_sclk
create_bd_port -dir O rx_sdo
create_bd_port -dir I -from 1 -to 0 rx_sdi
create_bd_port -dir O -from 15 -to 0 rx_db_o
create_bd_port -dir I -from 15 -to 0 rx_db_i
create_bd_port -dir O rx_db_t
create_bd_port -dir O rx_rd_n
create_bd_port -dir O rx_wr_n
set SER_PAR_N $ad_project_params(SER_PAR_N)
puts "build parameters: SER_PAR_N: $SER_PAR_N"
# control lines
create_bd_port -dir O rx_cnvst
create_bd_port -dir O rx_cs_n
create_bd_port -dir I rx_busy
# instantiation
ad_ip_instance axi_ad7616 axi_ad7616
ad_ip_parameter axi_ad7616 CONFIG.IF_TYPE $SI_OR_PI
# dma
ad_ip_instance axi_dmac axi_ad7616_dma
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_DEST 0
ad_ip_parameter axi_ad7616_dma CONFIG.CYCLIC 0
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 16
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_DEST 64
# interface connections
if {$SI_OR_PI == 0} {
ad_ip_instance axi_pwm_gen ad7616_pwm_gen
ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_PERIOD 100
ad_ip_parameter ad7616_pwm_gen CONFIG.PULSE_0_WIDTH 5
ad_ip_parameter ad7616_pwm_gen CONFIG.ASYNC_CLK_EN 0
ad_connect rx_sclk axi_ad7616/rx_sclk
ad_connect rx_sdo axi_ad7616/rx_sdo
ad_connect rx_sdi axi_ad7616/rx_sdi
ad_connect rx_cs_n axi_ad7616/rx_cs_n
# trigger to BUSY's negative edge
ad_connect rx_cnvst axi_ad7616/rx_cnvst
ad_connect rx_busy axi_ad7616/rx_busy
create_bd_cell -type module -reference sync_bits busy_sync
create_bd_cell -type module -reference ad_edge_detect busy_capture
set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture]
ad_connect sys_cpu_clk busy_capture/clk
ad_connect busy_capture/rst GND
ad_connect sys_cpu_clk busy_sync/out_clk
ad_connect busy_sync/in_bits rx_busy
ad_connect busy_sync/out_bits busy_capture/signal_in
if {$SER_PAR_N == 1} {
create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad7616_spi
source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
set data_width 16
set async_spi_clk 0
set num_cs 1
set num_sdi 2
set sdi_delay 1
set hier_spi_engine spi_ad7616
spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 32
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 1
ad_ip_parameter axi_ad7616_dma CONFIG.SYNC_TRANSFER_START 0
ad_ip_parameter axi_ad7616_dma CONFIG.AXI_SLICE_SRC 0
ad_ip_parameter axi_ad7616_dma CONFIG.AXI_SLICE_DEST 1
# interface connections
ad_connect sys_cpu_clk $hier_spi_engine/clk
ad_connect sys_cpu_resetn $hier_spi_engine/resetn
ad_connect $hier_spi_engine/m_spi ad7616_spi
ad_connect sys_cpu_clk axi_ad7616_dma/s_axis_aclk
ad_connect axi_ad7616_dma/s_axis $hier_spi_engine/m_axis_sample
ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn
ad_connect busy_capture/signal_out $hier_spi_engine/${hier_spi_engine}_offload/trigger
# interconnect
ad_cpu_interconnect 0x44A00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
# interrupts
ad_cpu_interrupt ps-12 mb-12 /$hier_spi_engine/irq
} else {
# data interfaces
create_bd_port -dir O -from 15 -to 0 rx_db_o
create_bd_port -dir I -from 15 -to 0 rx_db_i
create_bd_port -dir O rx_db_t
create_bd_port -dir O rx_rd_n
create_bd_port -dir O rx_wr_n
create_bd_port -dir O rx_cs_n
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC 16
ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 2
ad_ip_instance axi_ad7616 axi_ad7616
# interface connections
ad_connect rx_db_o axi_ad7616/rx_db_o
ad_connect rx_db_i axi_ad7616/rx_db_i
ad_connect rx_db_t axi_ad7616/rx_db_t
ad_connect rx_rd_n axi_ad7616/rx_rd_n
ad_connect rx_wr_n axi_ad7616/rx_wr_n
ad_connect rx_cs_n axi_ad7616/rx_cs_n
ad_connect rx_cnvst axi_ad7616/rx_cnvst
ad_connect rx_busy axi_ad7616/rx_busy
ad_connect sys_cpu_clk axi_ad7616_dma/fifo_wr_clk
ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en
ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din
ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync
ad_connect busy_capture/signal_out axi_ad7616/rx_trigger
ad_connect busy_sync/out_resetn sys_cpu_resetn
# interconnect
ad_cpu_interconnect 0x44A80000 axi_ad7616
}
# interface connections
ad_connect ad7616_pwm_gen/pwm_0 rx_cnvst
ad_connect $sys_cpu_clk ad7616_pwm_gen/s_axi_aclk
ad_connect sys_cpu_resetn ad7616_pwm_gen/s_axi_aresetn
ad_connect sys_cpu_clk axi_ad7616_dma/s_axi_aclk
ad_connect sys_cpu_clk axi_ad7616_dma/fifo_wr_clk
ad_connect axi_ad7616/adc_valid axi_ad7616_dma/fifo_wr_en
ad_connect axi_ad7616/adc_data axi_ad7616_dma/fifo_wr_din
ad_connect axi_ad7616/adc_sync axi_ad7616_dma/fifo_wr_sync
ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn
# interconnect
ad_cpu_interconnect 0x44A00000 axi_ad7616
ad_cpu_interconnect 0x44A30000 axi_ad7616_dma
ad_cpu_interconnect 0x44B00000 ad7616_pwm_gen
# memory interconnect
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_ad7616_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_ad7616_dma/m_dest_axi_aresetn
# interrupts
ad_cpu_interrupt ps-13 mb-12 axi_ad7616_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_ad7616/irq
ad_cpu_interrupt ps-13 mb-13 axi_ad7616_dma/irq

8
projects/ad7616_sdz/zc706/Makefile
View File

@ -12,14 +12,22 @@ M_DEPS += ../common/ad7616_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v
LIB_DEPS += axi_ad7616
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_pwm_gen
LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += sysid_rom
include ../../scripts/project-xilinx.mk

2
projects/ad7616_sdz/zc706/parallel_if_constr.xdc
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@ -27,7 +27,7 @@ set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS25} [get_ports adc_wr_
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P

12
projects/ad7616_sdz/zc706/serial_if_constr.xdc
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@ -7,15 +7,15 @@
# data interface
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_cs_n] ; ## FMC_LPC_LA04_N
# control lines
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P

7
projects/ad7616_sdz/zc706/system_bd.tcl
View File

@ -15,5 +15,12 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
# system level parameters
set SER_PAR_N $ad_project_params(SER_PAR_N)
adi_project_files ad7616_sdz_zc706 [list \
"../../../library/common/ad_edge_detect.v" \
"../../../library/util_cdc/sync_bits.v"]
source ../common/ad7616_bd.tcl

27
projects/ad7616_sdz/zc706/system_project.tcl
View File

@ -16,40 +16,43 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# How to use over-writable parameters from the environment:
#
# e.g.
# make SI_OR_PI=0
# make SER_PAR_N=1
#
# SI_OR_PI - Defines the interface type (serial OR parallel)
# SER_PAR_N - Defines the interface type (serial OR parallel)
# - Default value is 1
#
# LEGEND: Serial - 0
# Parallel - 1
# LEGEND: Serial - 1
# Parallel - 0
#
# NOTE : This switch is a 'hardware' switch. Please reimplenent the
# design if the variable has been changed.
# SL5 - mounted - Serial
# SL5 - unmounted - Parallel
#
##--------------------------------------------------------------
if {[info exists ::env(SI_OR_PI)]} {
set S_SI_OR_PI [get_env_param SI_OR_PI 0]
} elseif {![info exists SI_OR_PI]} {
set S_SI_OR_PI 0
if {[info exists ::env(SER_PAR_N)]} {
set S_SER_PAR_N [get_env_param SER_PAR_N 0]
} elseif {![info exists SER_PAR_N]} {
set S_SER_PAR_N 1
}
adi_project ad7616_sdz_zc706 0 [list \
SI_OR_PI $S_SI_OR_PI \
SER_PAR_N $S_SER_PAR_N \
]
adi_project_files ad7616_sdz_zc706 [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"]
switch $S_SI_OR_PI {
0 {
switch $S_SER_PAR_N {
1 {
adi_project_files ad7616_sdz_zc706 [list \
"system_top_si.v" \
"serial_if_constr.xdc"
]
}
1 {
0 {
adi_project_files ad7616_sdz_zc706 [list \
"system_top_pi.v" \
"parallel_if_constr.xdc"

25
projects/ad7616_sdz/zc706/system_top_pi.v
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@ -79,7 +79,7 @@ module system_top (
output adc_cs_n,
output adc_reset_n,
output adc_convst,
output adc_cnvst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
@ -96,8 +96,6 @@ module system_top (
wire [15:0] adc_db_o;
wire [15:0] adc_db_i;
genvar i;
// instantiations
ad_iobuf #(
@ -111,15 +109,16 @@ module system_top (
adc_seq_en, // 37
adc_chsel})); // 35:33
generate
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
ad_iobuf i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[i]),
.dio_o(adc_db_i[i]),
.dio_p(adc_db[i]));
end
endgenerate
assign gpio_i[63:44] = gpio_o[63:44];
assign gpio_i[32] = gpio_o[32];
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[15:0]),
.dio_o(adc_db_i[15:0]),
.dio_p(adc_db[15:0]));
ad_iobuf #(
.DATA_WIDTH(15)
@ -162,7 +161,7 @@ module system_top (
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.rx_cnvst (adc_convst),
.rx_cnvst (adc_cnvst),
.rx_cs_n (adc_cs_n),
.rx_busy (adc_busy),
.rx_db_o (adc_db_o),

22
projects/ad7616_sdz/zc706/system_top_si.v
View File

@ -73,13 +73,13 @@ module system_top (
inout iic_scl,
inout iic_sda,
output spi_sclk,
output spi_sdo,
input [ 1:0] spi_sdi,
output spi_cs_n,
output ad7616_spi_sclk,
output ad7616_spi_sdo,
input [ 1:0] ad7616_spi_sdi,
output ad7616_spi_cs_n,
output adc_reset_n,
output adc_convst,
output adc_cnvst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
@ -111,6 +111,8 @@ module system_top (
adc_chsel, // 35:33
adc_crcen})); // 32
assign gpio_i[63:44] = gpio_o[63:44];
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
@ -152,11 +154,11 @@ module system_top (
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.spdif (spdif),
.rx_sclk (spi_sclk),
.rx_sdo (spi_sdo),
.rx_sdi (spi_sdi),
.rx_cnvst (adc_convst),
.rx_cs_n (spi_cs_n),
.ad7616_spi_sdo (ad7616_spi_sdo),
.ad7616_spi_sdi (ad7616_spi_sdi),
.ad7616_spi_cs (ad7616_spi_cs),
.ad7616_spi_sclk (ad7616_spi_sclk),
.rx_cnvst (adc_cnvst),
.rx_busy (adc_busy));
endmodule

8
projects/ad7616_sdz/zed/Makefile
View File

@ -12,15 +12,23 @@ M_DEPS += ../common/ad7616_bd.tcl
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/util_cdc/sync_bits.v
M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_edge_detect.v
LIB_DEPS += axi_ad7616
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_pwm_gen
LIB_DEPS += axi_spdif_tx
LIB_DEPS += axi_sysid
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += sysid_rom
LIB_DEPS += util_i2c_mixer

2
projects/ad7616_sdz/zed/parallel_if_constr.xdc
View File

@ -28,7 +28,7 @@ set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports adc_wr_n
# control lines
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P

12
projects/ad7616_sdz/zed/serial_if_constr.xdc
View File

@ -7,15 +7,15 @@
# data interface
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports spi_cs_n] ; ## FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sclk] ; ## FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdo] ; ## FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[0]] ; ## FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_sdi[1]] ; ## FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports ad7616_spi_cs] ; ## FMC_LPC_LA04_N
# control lines
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_convst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports adc_cnvst] ; ## FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports adc_chsel[0]] ; ## FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports adc_chsel[1]] ; ## FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports adc_chsel[2]] ; ## FMC_LPC_LA25_P

7
projects/ad7616_sdz/zed/system_bd.tcl
View File

@ -15,5 +15,12 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
sysid_gen_sys_init_file
# system level parameters
set SER_PAR_N $ad_project_params(SER_PAR_N)
adi_project_files ad7616_sdz_zed [list \
"../../../library/common/ad_edge_detect.v" \
"../../../library/util_cdc/sync_bits.v"]
source ../common/ad7616_bd.tcl

31
projects/ad7616_sdz/zed/system_project.tcl
View File

@ -16,40 +16,43 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# How to use over-writable parameters from the environment:
#
# e.g.
# make SI_OR_PI=0
# make SER_PAR_N=0
#
# SI_OR_PI - Defines the interface type (serial OR parallel)
# SER_PAR_N - Defines the interface type (serial OR parallel)
# - Default value is 1
#
# LEGEND: Serial - 0
# Parallel - 1
# LEGEND: Serial - 1
# Parallel - 0
#
# NOTE : This switch is a 'hardware' switch. Please reimplenent the
# design if the variable has been changed.
# NOTE : This switch is a 'hardware' switch. Please rebuild the design if the
# variable has been changed.
# SL5 - mounted - Serial
# SL5 - unmounted - Parallel
#
##--------------------------------------------------------------
if {[info exists ::env(SI_OR_PI)]} {
set S_SI_OR_PI [get_env_param SI_OR_PI 0]
} elseif {![info exists SI_OR_PI]} {
set S_SI_OR_PI 0
if {[info exists ::env(SER_PAR_N)]} {
set S_SER_PAR_N [get_env_param SER_PAR_N 0]
} elseif {![info exists SER_PAR_N]} {
set S_SER_PAR_N 1
}
adi_project ad7616_sdz_zed 0 [list \
SI_OR_PI $S_SI_OR_PI \
SER_PAR_N $S_SER_PAR_N \
]
adi_project_files ad7616_sdz_zed [list \
"$ad_hdl_dir/library/common/ad_iobuf.v" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"]
switch $S_SI_OR_PI {
0 {
switch $S_SER_PAR_N {
1 {
adi_project_files ad7616_sdz_zed [list \
"system_top_si.v" \
"serial_if_constr.xdc"
]
}
1 {
0 {
adi_project_files ad7616_sdz_zed [list \
"system_top_pi.v" \
"parallel_if_constr.xdc"

21
projects/ad7616_sdz/zed/system_top_pi.v
View File

@ -89,7 +89,7 @@ module system_top (
output adc_cs_n,
output adc_reset_n,
output adc_convst,
output adc_cnvst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
@ -130,16 +130,15 @@ module system_top (
assign gpio_i[63:44] = gpio_o[63:44];
assign gpio_i[40:38] = gpio_o[40:38];
assign gpio_i[36] = gpio_o[36];
assign gpio_i[32] = gpio_o[32];
generate
for (i = 0; i < 16; i = i + 1) begin: adc_db_io
ad_iobuf i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[i]),
.dio_o(adc_db_i[i]),
.dio_p(adc_db[i]));
end
endgenerate
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf_adc_db (
.dio_t(adc_db_t),
.dio_i(adc_db_o[15:0]),
.dio_o(adc_db_i[15:0]),
.dio_p(adc_db[15:0]));
ad_iobuf #(
.DATA_WIDTH(32)
@ -210,7 +209,7 @@ module system_top (
.iic_mux_sda_t (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.rx_cnvst (adc_convst),
.rx_cnvst (adc_cnvst),
.rx_cs_n (adc_cs_n),
.rx_busy (adc_busy),
.rx_db_o (adc_db_o),

22
projects/ad7616_sdz/zed/system_top_si.v
View File

@ -83,13 +83,13 @@ module system_top (
input otg_vbusoc,
output spi_sclk,
output spi_sdo,
input [ 1:0] spi_sdi,
output spi_cs_n,
output ad7616_spi_sclk,
output ad7616_spi_sdo,
input [ 1:0] ad7616_spi_sdi,
output ad7616_spi_cs,
output adc_reset_n,
output adc_convst,
output adc_cnvst,
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
@ -198,11 +198,11 @@ module system_top (
.iic_mux_sda_t (iic_mux_sda_t_s),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif),
.rx_cnvst (adc_convst),
.rx_sclk (spi_sclk),
.rx_sdo (spi_sdo),
.rx_sdi (spi_sdi),
.rx_cs_n (spi_cs_n),
.rx_busy (adc_busy));
.ad7616_spi_sdo (ad7616_spi_sdo),
.ad7616_spi_sdi (ad7616_spi_sdi),
.ad7616_spi_cs (ad7616_spi_cs),
.ad7616_spi_sclk (ad7616_spi_sclk),
.rx_busy (adc_busy),
.rx_cnvst (adc_cnvst));
endmodule