diff --git a/library/jesd204/jesd204_tx/Makefile b/library/jesd204/jesd204_tx/Makefile
index ba45e9419..a10af56b1 100644
--- a/library/jesd204/jesd204_tx/Makefile
+++ b/library/jesd204/jesd204_tx/Makefile
@@ -10,7 +10,9 @@ GENERIC_DEPS += jesd204_tx_ctrl.v
GENERIC_DEPS += jesd204_tx_lane.v
XILINX_DEPS += jesd204_tx_constr.ttcl
+XILINX_DEPS += jesd204_tx_header.v
XILINX_DEPS += jesd204_tx_ip.tcl
+XILINX_DEPS += jesd204_tx_lane_64b.v
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
@@ -32,6 +34,7 @@ INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v
INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v
INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v
+INTEL_DEPS += ../jesd204_common/pipeline_stage.v
INTEL_DEPS += jesd204_tx_constr.sdc
INTEL_DEPS += jesd204_tx_hw.tcl
diff --git a/library/jesd204/jesd204_tx/jesd204_tx.v b/library/jesd204/jesd204_tx/jesd204_tx.v
index 3e670d88a..6b9554274 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx.v
@@ -47,13 +47,17 @@
module jesd204_tx #(
parameter NUM_LANES = 1,
parameter NUM_LINKS = 1,
- parameter NUM_OUTPUT_PIPELINE = 0
+ parameter NUM_OUTPUT_PIPELINE = 0,
+ parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
+ /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
+ parameter DATA_PATH_WIDTH = LINK_MODE[1] ? 8 : 4
) (
input clk,
input reset,
- output [32*NUM_LANES-1:0] phy_data,
- output [4*NUM_LANES-1:0] phy_charisk,
+ output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] phy_data,
+ output [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_charisk,
+ output [2*NUM_LANES-1:0] phy_header,
input sysref,
output lmfc_edge,
@@ -61,7 +65,7 @@ module jesd204_tx #(
input [NUM_LINKS-1:0] sync,
- input [32*NUM_LANES-1:0] tx_data,
+ input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_data,
output tx_ready,
input tx_valid,
@@ -92,8 +96,6 @@ module jesd204_tx #(
output [1:0] status_state
);
-/* Only 4 is supported at the moment */
-localparam DATA_PATH_WIDTH = 4;
localparam MAX_OCTETS_PER_FRAME = 8;
localparam MAX_OCTETS_PER_MULTIFRAME =
@@ -111,20 +113,17 @@ localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES;
localparam CW = DATA_PATH_WIDTH * NUM_LANES;
+localparam HW = 2 * NUM_LANES;
-wire eof_gen_reset;
-wire [DATA_PATH_WIDTH-1:0] eof;
-wire eomf;
-wire [NUM_LANES-1:0] lane_cgs_enable;
-
-wire [DW-1:0] ilas_data;
-wire [DATA_PATH_WIDTH-1:0] ilas_charisk;
-
-wire cfg_generate_eomf = 1'b1;
wire [DW-1:0] phy_data_r;
wire [CW-1:0] phy_charisk_r;
+wire [HW-1:0] phy_header_r;
+
+wire lmc_edge;
+wire lmc_quarter_edge;
+wire eoemb;
jesd204_lmfc i_lmfc (
.clk(clk),
@@ -142,9 +141,28 @@ jesd204_lmfc i_lmfc (
.lmfc_edge(lmfc_edge),
.lmfc_clk(lmfc_clk),
- .lmfc_counter()
+ .lmfc_counter(),
+ .lmc_edge(lmc_edge),
+ .lmc_quarter_edge(lmc_quarter_edge),
+ .eoemb(eoemb)
);
+generate
+genvar i;
+
+if (LINK_MODE[0] == 1) begin : mode_8b10b
+
+wire eof_gen_reset;
+wire [DATA_PATH_WIDTH-1:0] eof;
+wire eomf;
+
+wire [NUM_LANES-1:0] lane_cgs_enable;
+
+wire [DW-1:0] ilas_data;
+wire [DATA_PATH_WIDTH-1:0] ilas_charisk;
+
+wire cfg_generate_eomf = 1'b1;
+
jesd204_tx_ctrl #(
.NUM_LANES(NUM_LANES),
.NUM_LINKS(NUM_LINKS),
@@ -198,23 +216,8 @@ jesd204_eof_generator #(
.eomf(eomf)
);
-pipeline_stage #(
- .WIDTH(CW + DW),
- .REGISTERED(NUM_OUTPUT_PIPELINE)
-) i_output_pipeline_stage (
- .clk(clk),
- .in({
- phy_data_r,
- phy_charisk_r
- }),
- .out({
- phy_data,
- phy_charisk
- })
-);
-generate
-genvar i;
+
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
localparam D_START = i * DATA_PATH_WIDTH*8;
@@ -244,6 +247,77 @@ for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
.cfg_disable_scrambler(cfg_disable_scrambler)
);
end
+
+assign phy_header_r = 'h0;
+
+end
+
+if (LINK_MODE[1] == 1) begin : mode_64b66b
+ reg tx_ready_loc;
+
+ for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
+ localparam D_START = i * DATA_PATH_WIDTH*8;
+ localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
+ localparam H_START = i * 2;
+ localparam H_STOP = H_START + 2 -1;
+ jesd204_tx_lane_64b i_lane(
+ .clk(clk),
+ .reset(reset),
+
+ .tx_data(tx_data[D_STOP:D_START]),
+ .tx_ready(tx_ready_loc),
+
+ .phy_data(phy_data_r[D_STOP:D_START]),
+ .phy_header(phy_header_r[H_STOP:H_START]),
+
+ .lmc_edge(lmc_edge),
+ .lmc_quarter_edge(lmc_quarter_edge),
+ .eoemb(eoemb),
+
+ .cfg_disable_scrambler(cfg_disable_scrambler),
+ .cfg_header_mode(2'b0),
+ .cfg_lane_disable(cfg_lanes_disable[i])
+ );
+ end
+
+ always @(posedge clk) begin
+ if (reset) begin
+ tx_ready_loc <= 1'b0;
+ end else if (lmfc_edge) begin
+ tx_ready_loc <= 1'b1;
+ end
+ end
+
+ assign tx_ready = tx_ready_loc;
+ // Link considered in DATA phase when SYSREF received and LEMC clock started
+ // running
+ assign status_state = {2{tx_ready_loc}};
+
+
+ assign phy_charisk_r = 'h0;
+ assign ilas_config_rd = 'h0;
+ assign ilas_config_addr = 'h0;
+ assign status_sync = 'h0;
+
+end
+
endgenerate
+pipeline_stage #(
+ .WIDTH(CW + DW + HW),
+ .REGISTERED(NUM_OUTPUT_PIPELINE)
+) i_output_pipeline_stage (
+ .clk(clk),
+ .in({
+ phy_data_r,
+ phy_charisk_r,
+ phy_header_r
+ }),
+ .out({
+ phy_data,
+ phy_charisk,
+ phy_header
+ })
+);
+
endmodule
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_header.v b/library/jesd204/jesd204_tx/jesd204_tx_header.v
new file mode 100644
index 000000000..347247343
--- /dev/null
+++ b/library/jesd204/jesd204_tx/jesd204_tx_header.v
@@ -0,0 +1,108 @@
+//
+// The ADI JESD204 Core is released under the following license, which is
+// different than all other HDL cores in this repository.
+//
+// Please read this, and understand the freedoms and responsibilities you have
+// by using this source code/core.
+//
+// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+//
+// This core is free software, you can use run, copy, study, change, ask
+// questions about and improve this core. Distribution of source, or resulting
+// binaries (including those inside an FPGA or ASIC) require you to release the
+// source of the entire project (excluding the system libraries provide by the
+// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+// License version 2 as published by the Free Software Foundation.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License version 2
+// along with this source code, and binary. If not, see
+// .
+//
+// Commercial licenses (with commercial support) of this JESD204 core are also
+// available under terms different than the General Public License. (e.g. they
+// do not require you to accompany any image (FPGA or ASIC) using the JESD204
+// core with any corresponding source code.) For these alternate terms you must
+// purchase a license from Analog Devices Technology Licensing Office. Users
+// interested in such a license should contact jesd204-licensing@analog.com for
+// more information. This commercial license is sub-licensable (if you purchase
+// chips from Analog Devices, incorporate them into your PCB level product, and
+// purchase a JESD204 license, end users of your product will also have a
+// license to use this core in a commercial setting without releasing their
+// source code).
+//
+// In addition, we kindly ask you to acknowledge ADI in any program, application
+// or publication in which you use this JESD204 HDL core. (You are not required
+// to do so; it is up to your common sense to decide whether you want to comply
+// with this request or not.) For general publications, we suggest referencing :
+// “The design and implementation of the JESD204 HDL Core used in this project
+// is copyright © 2016-2017, Analog Devices, Inc.”
+//
+
+`timescale 1ns/100ps
+
+module jesd204_tx_header (
+ input clk,
+ input reset,
+
+ input [1:0] cfg_header_mode,
+
+ input lmc_edge,
+ input lmc_quarter_edge,
+
+ // Header content to be sent must be valid during lmc_edge
+ input eoemb,
+ input [2:0] crc3,
+ input [11:0] crc12,
+ input [25:0] fec,
+ input [18:0] cmd,
+
+ output [1:0] header
+
+);
+
+ reg header_bit;
+ reg [31:0] sync_word = 'h0;
+
+
+ always @(posedge clk) begin
+ if (reset) begin
+ sync_word <= 'h0;
+ end else if (lmc_edge) begin
+ case (cfg_header_mode)
+ // CRC-12
+ 2'b00 : sync_word <= {crc12[11:9],1'b1,crc12[8:6],1'b1,
+ crc12[5:3],1'b1,crc12[2:0],1'b1,
+ cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
+ cmd[2:0],5'b00001};
+ // CRC-3
+ 2'b01 : sync_word <= { crc3[2:0],1'b1,cmd[6:4],1'b1,
+ 3'b000,1'b1,cmd[3:1],1'b1,
+ 3'b000,1'b1,cmd[0],1'b1,eoemb,1'b1,
+ 3'b000,5'b00001};
+ // FEC
+ 2'b10 : sync_word <= { fec[25:18],
+ fec[17:10],
+ fec[9:4],eoemb,fec[3],
+ fec[2:0],5'b00001};
+ // Stand alone command
+ 2'b11 : sync_word <= { cmd[18:16],1'b1,cmd[15:13],1'b1,
+ cmd[12:10],1'b1,cmd[9:7],1'b1,
+ cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
+ cmd[2:0],5'b00001};
+ endcase
+ end else begin
+ if (lmc_quarter_edge && cfg_header_mode == 2'b01) begin
+ sync_word <= {crc3[2],crc3[1],crc3[0],sync_word[27:0],1'b0};
+ end else begin
+ sync_word <= {sync_word[30:0],1'b0};
+ end
+ end
+ end
+
+ assign header = {~sync_word[31],sync_word[31]};
+
+endmodule
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
index b3f04ef4e..4518d7356 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
@@ -48,6 +48,8 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create jesd204_tx
adi_ip_files jesd204_tx [list \
"jesd204_tx_lane.v" \
+ "jesd204_tx_lane_64b.v" \
+ "jesd204_tx_header.v" \
"jesd204_tx_ctrl.v" \
"jesd204_tx_constr.ttcl" \
"jesd204_tx.v"
@@ -77,8 +79,9 @@ adi_add_multi_bus 16 "tx_phy" "master" \
"xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
"xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \
[list \
- {"phy_data" "txdata" 32} \
- { "phy_charisk" "txcharisk" 4} \
+ { "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
+ { "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
+ { "phy_header" "txheader" 2} \
] \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
@@ -136,9 +139,43 @@ adi_add_bus "tx_ctrl" "slave" \
adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \
"reset"
+adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
+ "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
+
+adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
+ "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
+
+adi_set_ports_dependency "sync" \
+ "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
+
+
set cc [ipx::current_core]
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
+# Link layer mode
+set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
+ipgui::move_param -component $cc -order 0 $p -parent $page0
+set_property -dict [list \
+ "display_name" "Link Layer mode" \
+ "tooltip" "Link Layer mode" \
+ "widget" "comboBox" \
+] $p
+
+set_property -dict [list \
+ value_validation_type pairs \
+ value_validation_pairs {64B66B 2 8B10B 1} \
+] [ipx::get_user_parameters $p -of_objects $cc]
+
+
+# Data width selection
+set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
+set_property -dict [list \
+ enablement_value false \
+ value_tcl_expr {expr $LINK_MODE*4} \
+] $param
+
+
+# SYSREF IOB placement
set param [ipx::add_user_parameter SYSREF_IOB $cc]
set_property -dict {value_resolve_type user value_format bool value true} $param
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
new file mode 100644
index 000000000..6cccf1b0d
--- /dev/null
+++ b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
@@ -0,0 +1,143 @@
+//
+// The ADI JESD204 Core is released under the following license, which is
+// different than all other HDL cores in this repository.
+//
+// Please read this, and understand the freedoms and responsibilities you have
+// by using this source code/core.
+//
+// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+//
+// This core is free software, you can use run, copy, study, change, ask
+// questions about and improve this core. Distribution of source, or resulting
+// binaries (including those inside an FPGA or ASIC) require you to release the
+// source of the entire project (excluding the system libraries provide by the
+// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+// License version 2 as published by the Free Software Foundation.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License version 2
+// along with this source code, and binary. If not, see
+// .
+//
+// Commercial licenses (with commercial support) of this JESD204 core are also
+// available under terms different than the General Public License. (e.g. they
+// do not require you to accompany any image (FPGA or ASIC) using the JESD204
+// core with any corresponding source code.) For these alternate terms you must
+// purchase a license from Analog Devices Technology Licensing Office. Users
+// interested in such a license should contact jesd204-licensing@analog.com for
+// more information. This commercial license is sub-licensable (if you purchase
+// chips from Analog Devices, incorporate them into your PCB level product, and
+// purchase a JESD204 license, end users of your product will also have a
+// license to use this core in a commercial setting without releasing their
+// source code).
+//
+// In addition, we kindly ask you to acknowledge ADI in any program, application
+// or publication in which you use this JESD204 HDL core. (You are not required
+// to do so; it is up to your common sense to decide whether you want to comply
+// with this request or not.) For general publications, we suggest referencing :
+// “The design and implementation of the JESD204 HDL Core used in this project
+// is copyright © 2016-2017, Analog Devices, Inc.”
+//
+
+`timescale 1ns/100ps
+
+module jesd204_tx_lane_64b (
+ input clk,
+ input reset,
+
+ input [63:0] tx_data,
+ input tx_ready,
+
+ output reg [63:0] phy_data,
+ output [1:0] phy_header,
+
+ input lmc_edge,
+ input lmc_quarter_edge,
+ input eoemb,
+
+ // Scrambling mandatory in 64bxxb, keep this for debugging purposes
+ input cfg_disable_scrambler,
+ input [1:0] cfg_header_mode,
+ input cfg_lane_disable
+
+);
+
+reg [63:0] scrambled_data;
+reg lmc_edge_d1 = 'b0;
+reg lmc_edge_d2 = 'b0;
+reg lmc_quarter_edge_d1 = 'b0;
+reg lmc_quarter_edge_d2 = 'b0;
+reg tx_ready_d1 = 'b0;
+
+wire [63:0] tx_data_msb_s;
+wire [63:0] scrambled_data_r;
+wire [11:0] crc12;
+
+/* Reorder octets MSB first */
+genvar i;
+generate
+ for (i = 0; i < 64; i = i + 8) begin: g_link_data
+ assign tx_data_msb_s[i+:8] = tx_data[64-1-i-:8];
+ end
+endgenerate
+
+jesd204_scrambler_64b #(
+ .WIDTH(64),
+ .DESCRAMBLE(0)
+) i_scrambler (
+ .clk(clk),
+ .reset(reset),
+ .enable(~cfg_disable_scrambler),
+ .data_in(tx_data_msb_s),
+ .data_out(scrambled_data_r)
+);
+
+always @(posedge clk) begin
+ lmc_edge_d1 <= lmc_edge;
+ lmc_edge_d2 <= lmc_edge_d1;
+ lmc_quarter_edge_d1 <= lmc_quarter_edge;
+ lmc_quarter_edge_d2 <= lmc_quarter_edge_d1;
+end
+
+always @(posedge clk) begin
+ scrambled_data <= scrambled_data_r;
+ phy_data <= scrambled_data;
+end
+
+always @(posedge clk) begin
+ tx_ready_d1 <= tx_ready;
+end
+
+jesd204_crc12 i_crc12 (
+ .clk(clk),
+ .reset(~tx_ready_d1),
+ .init(lmc_edge_d2),
+ .data_in(scrambled_data),
+ .crc12(crc12)
+);
+
+jesd204_tx_header i_header_gen (
+ .clk(clk),
+ .reset(~tx_ready | cfg_lane_disable),
+
+ .cfg_header_mode(cfg_header_mode),
+
+ .lmc_edge(lmc_edge_d2),
+ .lmc_quarter_edge(lmc_quarter_edge_d2),
+
+ // Header content to be sent must be valid during lmc_edge
+ .eoemb(eoemb),
+ .crc3(3'b0),
+ .crc12(crc12),
+ .fec(26'b0),
+ .cmd(19'b0),
+
+ .header(phy_header)
+
+);
+
+
+endmodule
diff --git a/library/jesd204/tb/tx_64b_tb b/library/jesd204/tb/tx_64b_tb
new file mode 100755
index 000000000..37cc47dc8
--- /dev/null
+++ b/library/jesd204/tb/tx_64b_tb
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+SOURCE="tx_64b_tb.v"
+SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler_64b.v ../jesd204_common/jesd204_crc12.v"
+SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_lane_64b.v ../jesd204_tx/jesd204_tx_header.v"
+SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v"
+SOURCE+=" ../../util_cdc/sync_bits.v"
+SOURCE+=" ../jesd204_common/pipeline_stage.v"
+
+cd `dirname $0`
+source run_tb.sh
diff --git a/library/jesd204/tb/tx_64b_tb.v b/library/jesd204/tb/tx_64b_tb.v
new file mode 100644
index 000000000..4c56e8703
--- /dev/null
+++ b/library/jesd204/tb/tx_64b_tb.v
@@ -0,0 +1,176 @@
+//
+// The ADI JESD204 Core is released under the following license, which is
+// different than all other HDL cores in this repository.
+//
+// Please read this, and understand the freedoms and responsibilities you have
+// by using this source code/core.
+//
+// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
+//
+// This core is free software, you can use run, copy, study, change, ask
+// questions about and improve this core. Distribution of source, or resulting
+// binaries (including those inside an FPGA or ASIC) require you to release the
+// source of the entire project (excluding the system libraries provide by the
+// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
+// License version 2 as published by the Free Software Foundation.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License version 2
+// along with this source code, and binary. If not, see
+// .
+//
+// Commercial licenses (with commercial support) of this JESD204 core are also
+// available under terms different than the General Public License. (e.g. they
+// do not require you to accompany any image (FPGA or ASIC) using the JESD204
+// core with any corresponding source code.) For these alternate terms you must
+// purchase a license from Analog Devices Technology Licensing Office. Users
+// interested in such a license should contact jesd204-licensing@analog.com for
+// more information. This commercial license is sub-licensable (if you purchase
+// chips from Analog Devices, incorporate them into your PCB level product, and
+// purchase a JESD204 license, end users of your product will also have a
+// license to use this core in a commercial setting without releasing their
+// source code).
+//
+// In addition, we kindly ask you to acknowledge ADI in any program, application
+// or publication in which you use this JESD204 HDL core. (You are not required
+// to do so; it is up to your common sense to decide whether you want to comply
+// with this request or not.) For general publications, we suggest referencing :
+// “The design and implementation of the JESD204 HDL Core used in this project
+// is copyright © 2016-2017, Analog Devices, Inc.”
+//
+
+`timescale 1ns/100ps
+
+module tx_64b_tb;
+ parameter VCD_FILE = "tx_tb.vcd";
+ parameter NUM_LANES = 1;
+ parameter NUM_LINKS = 1;
+ parameter OCTETS_PER_FRAME = 4;
+ parameter FRAMES_PER_MULTIFRAME = 32;
+
+ `include "tb_base.v"
+
+
+ reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
+ reg [31:0] counter = 'h00;
+ reg [63:0] tx_data = 'h00000000;
+
+ wire tx_ready;
+ wire tx_valid = 1'b1;
+ wire [NUM_LANES-1:0] cfg_lanes_disable;
+ wire [NUM_LINKS-1:0] cfg_links_disable;
+ wire [7:0] cfg_beats_per_multiframe;
+ wire [7:0] cfg_octets_per_frame;
+ wire [7:0] cfg_lmfc_offset;
+ wire cfg_sysref_oneshot;
+ wire cfg_sysref_disable;
+ wire cfg_continuous_cgs;
+ wire cfg_continuous_ilas;
+ wire cfg_skip_ilas;
+ wire [7:0] cfg_mframes_per_ilas;
+ wire cfg_disable_char_replacement;
+ wire cfg_disable_scrambler;
+ wire tx_ilas_config_rd;
+ wire [1:0] tx_ilas_config_addr;
+ wire [32*NUM_LANES-1:0] tx_ilas_config_data;
+
+ always @(posedge clk) begin
+ if (reset == 1'b1) begin
+ tx_data <= 'h00000000;
+ end else if (tx_ready == 1'b1) begin
+ tx_data <= tx_data + 1'b1;
+ end
+ end
+
+ /* Generate independent SYNCs
+ *
+ * Each SYNC will be asserted/deasserted at different clock edges.
+ * The assertion/deassertion order: first SYNC[0], ..., last SYNC[NUM_LINKS-1]
+ */
+ always @(posedge clk) begin
+ counter <= counter + 1'b1;
+ end
+
+ genvar i;
+ generate
+ for (i=1; i<=NUM_LINKS; i=i+1) begin: SYNC_GENERATOR
+ always @(posedge clk) begin
+ if (counter >= (32'h100 | (i << 4)) && counter <= (32'h300 | (i << 4))) begin
+ sync[i-1] <= 1'b0;
+ end else begin
+ sync[i-1] <= 1'b1;
+ end
+ end
+ end
+ endgenerate
+
+ // DUT with static configuration
+
+ jesd204_tx_static_config #(
+ .NUM_LANES(NUM_LANES),
+ .NUM_LINKS(NUM_LINKS),
+ .OCTETS_PER_FRAME(OCTETS_PER_FRAME),
+ .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME)
+ ) i_cfg (
+ .clk(clk),
+
+ .cfg_lanes_disable(cfg_lanes_disable),
+ .cfg_links_disable(cfg_links_disable),
+ .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
+ .cfg_octets_per_frame(cfg_octets_per_frame),
+ .cfg_lmfc_offset(cfg_lmfc_offset),
+ .cfg_continuous_cgs(cfg_continuous_cgs),
+ .cfg_continuous_ilas(cfg_continuous_ilas),
+ .cfg_skip_ilas(cfg_skip_ilas),
+ .cfg_mframes_per_ilas(cfg_mframes_per_ilas),
+ .cfg_disable_char_replacement(cfg_disable_char_replacement),
+ .cfg_disable_scrambler(cfg_disable_scrambler),
+ .cfg_sysref_oneshot(cfg_sysref_oneshot),
+ .cfg_sysref_disable(cfg_sysref_disable),
+
+ .ilas_config_rd(tx_ilas_config_rd),
+ .ilas_config_addr(tx_ilas_config_addr),
+ .ilas_config_data(tx_ilas_config_data)
+ );
+
+ jesd204_tx #(
+ .NUM_LANES(NUM_LANES),
+ .NUM_LINKS(NUM_LINKS),
+ .LINK_MODE(2)
+ ) i_tx (
+ .clk(clk),
+ .reset(reset),
+
+ .cfg_lanes_disable(cfg_lanes_disable),
+ .cfg_links_disable(cfg_links_disable),
+ .cfg_beats_per_multiframe(cfg_beats_per_multiframe),
+ .cfg_octets_per_frame(cfg_octets_per_frame),
+ .cfg_lmfc_offset(cfg_lmfc_offset),
+ .cfg_continuous_cgs(cfg_continuous_cgs),
+ .cfg_continuous_ilas(cfg_continuous_ilas),
+ .cfg_skip_ilas(cfg_skip_ilas),
+ .cfg_mframes_per_ilas(cfg_mframes_per_ilas),
+ .cfg_disable_char_replacement(cfg_disable_char_replacement),
+ .cfg_disable_scrambler(cfg_disable_scrambler),
+ .cfg_sysref_oneshot(cfg_sysref_oneshot),
+ .cfg_sysref_disable(cfg_sysref_disable),
+
+ .ilas_config_rd(tx_ilas_config_rd),
+ .ilas_config_addr(tx_ilas_config_addr),
+ .ilas_config_data(tx_ilas_config_data),
+
+ .ctrl_manual_sync_request (1'b0),
+
+ .tx_ready(tx_ready),
+ .tx_valid(tx_valid),
+ .tx_data({NUM_LANES{tx_data}}),
+
+ .sync(sync),
+ .sysref(sysref)
+ );
+
+
+endmodule