From da28ee3cce4f5b15e2faddd25c42efbb495894cf Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 19 Jan 2018 14:45:38 +0100 Subject: [PATCH] axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity Commit ff50963c7f83 ("axi_ad9361- altera/xilinx reconcile- may be broken- do not use") inverted the polarity of the TX feedback clock. This exposed some issues in the existing drivers which can cause the interface tuning to fail randomly under certain conditions. To keep backwards compatibility with existing drivers restore the previous behavior. A separate fix will be applied to the drivers that resolves the issue that has been exposed by the polarity inversion. So that interface calibration works reliably under all conditions. Signed-off-by: Lars-Peter Clausen --- library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index 8f50a42a4..b3a54eaab 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -366,7 +366,7 @@ module axi_ad9361_lvds_if #( end always @(posedge clk) begin - tx_clk_p <= {dac_clksel, ~dac_clksel}; + tx_clk_p <= {~dac_clksel, dac_clksel}; end always @(posedge clk) begin