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axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity 

Commit ff50963c7f ("axi_ad9361- altera/xilinx reconcile- may be broken-
do not use") inverted the polarity of the TX feedback clock.

This exposed some issues in the existing drivers which can cause the
interface tuning to fail randomly under certain conditions.

To keep backwards compatibility with existing drivers restore the previous
behavior.

A separate fix will be applied to the drivers that resolves the issue that
has been exposed by the polarity inversion. So that interface calibration
works reliably under all conditions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-01-19 14:45:38 +01:00
parent 92321f0534
commit da28ee3cce
1 changed files with 1 additions and 1 deletions
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library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
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@ -366,7 +366,7 @@ module axi_ad9361_lvds_if #(
end
always @(posedge clk) begin
tx_clk_p <= {dac_clksel, ~dac_clksel};
tx_clk_p <= {~dac_clksel, dac_clksel};
end
always @(posedge clk) begin