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library: 2015.2 updates 

IPI bus interface names have changed in this new release.
main
Istvan Csomortani 2015-08-25 09:13:24 +03:00
parent 78cf0fce0e
commit da315eb6c0
4 changed files with 2 additions and 8 deletions
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2
library/axi_clkgen/axi_clkgen_ip.tcl
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@ -15,7 +15,7 @@ adi_ip_files axi_clkgen [list \
adi_ip_properties axi_clkgen adi_ip_properties axi_clkgen
ipx::remove_bus_interface {signal_clock} [ipx::current_core] ipx::remove_bus_interface {clk} [ipx::current_core]
ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core] ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
#set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \ #set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \

3
library/axi_dmac/axi_dmac_ip.tcl
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@ -33,9 +33,6 @@ adi_ip_add_core_dependencies { \
analog.com:user:util_axis_fifo:1.0 \ analog.com:user:util_axis_fifo:1.0 \
} }
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
adi_add_bus "s_axis" "slave" \ adi_add_bus "s_axis" "slave" \
"xilinx.com:interface:axis_rtl:1.0" \ "xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \ "xilinx.com:interface:axis:1.0" \

3
library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
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@ -22,9 +22,6 @@ adi_ip_add_core_dependencies { \
analog.com:user:util_axis_fifo:1.0 \ analog.com:user:util_axis_fifo:1.0 \
} }
set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \
[ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]
adi_add_bus "spi_engine_ctrl" "master" \ adi_add_bus "spi_engine_ctrl" "master" \
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \ "analog.com:interface:spi_engine_ctrl_rtl:1.0" \
"analog.com:interface:spi_engine_ctrl:1.0" \ "analog.com:interface:spi_engine_ctrl:1.0" \

2
library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl
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@ -17,7 +17,7 @@ adi_ip_constraints util_gmii_to_rgmii [list \
ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core]
set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]] set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]]
ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core]
set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces signal_reset -of_objects [ipx::current_core]]] set_property value ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of_objects [ipx::get_bus_interfaces reset -of_objects [ipx::current_core]]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \
[ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]]