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ad6766evb: Use new pack infrastructure 

Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-02-12 19:06:43 +01:00 committed by Adrian Costina
parent 9b919636ca
commit da50d682c5
3 changed files with 17 additions and 16 deletions
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29
projects/ad6676evb/common/ad6676evb_bd.tcl
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@ -15,8 +15,11 @@ adi_axi_jesd204_rx_create axi_ad6676_jesd 2
ad_ip_instance axi_ad6676 axi_ad6676_core
ad_ip_instance util_cpack axi_ad6676_cpack
ad_ip_parameter axi_ad6676_cpack CONFIG.NUM_OF_CHANNELS 2
ad_ip_instance util_cpack2 axi_ad6676_cpack { \
NUM_OF_CHANNELS 2 \
SAMPLES_PER_CHANNEL 2 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance axi_dmac axi_ad6676_dma
ad_ip_parameter axi_ad6676_dma CONFIG.DMA_TYPE_SRC 2
@ -62,19 +65,17 @@ ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_core/rx_clk
ad_connect util_ad6676_xcvr/rx_out_clk_0 rx_core_clk
ad_connect axi_ad6676_jesd/rx_sof axi_ad6676_core/rx_sof
ad_connect axi_ad6676_jesd/rx_data_tdata axi_ad6676_core/rx_data
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/adc_clk
ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/adc_rst
ad_connect axi_ad6676_core/adc_enable_0 axi_ad6676_cpack/adc_enable_0
ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/adc_valid_0
ad_connect axi_ad6676_core/adc_data_0 axi_ad6676_cpack/adc_data_0
ad_connect axi_ad6676_core/adc_enable_1 axi_ad6676_cpack/adc_enable_1
ad_connect axi_ad6676_core/adc_valid_1 axi_ad6676_cpack/adc_valid_1
ad_connect axi_ad6676_core/adc_data_1 axi_ad6676_cpack/adc_data_1
ad_connect util_ad6676_xcvr/rx_out_clk_0 axi_ad6676_cpack/clk
ad_connect axi_ad6676_jesd_rstgen/peripheral_reset axi_ad6676_cpack/reset
ad_connect axi_ad6676_core/adc_dovf axi_ad6676_cpack/fifo_wr_overflow
ad_connect axi_ad6676_core/adc_valid_0 axi_ad6676_cpack/fifo_wr_en
for {set i 0} {$i < 2} {incr i} {
ad_connect axi_ad6676_core/adc_enable_${i} axi_ad6676_cpack/enable_${i}
ad_connect axi_ad6676_core/adc_data_${i} axi_ad6676_cpack/fifo_wr_data_${i}
}
ad_connect axi_ad6676_core/adc_clk axi_ad6676_dma/fifo_wr_clk
ad_connect axi_ad6676_dma/fifo_wr_en axi_ad6676_cpack/adc_valid
ad_connect axi_ad6676_dma/fifo_wr_sync axi_ad6676_cpack/adc_sync
ad_connect axi_ad6676_dma/fifo_wr_din axi_ad6676_cpack/adc_data
ad_connect axi_ad6676_core/adc_dovf axi_ad6676_dma/fifo_wr_overflow
ad_connect axi_ad6676_dma/fifo_wr axi_ad6676_cpack/packed_fifo_wr
# interconnect (cpu)

2
projects/ad6676evb/vc707/Makefile
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@ -17,7 +17,7 @@ LIB_DEPS += axi_ad6676
LIB_DEPS += axi_dmac
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += util_cpack
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr

2
projects/ad6676evb/zc706/Makefile
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@ -19,7 +19,7 @@ LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_spdif_tx
LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += util_cpack
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += xilinx/axi_adxcvr
LIB_DEPS += xilinx/util_adxcvr