From da546771013d0e5c7664f121d782a0bc3f32d164 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 18 Apr 2018 09:00:00 +0100 Subject: [PATCH] usrpe31x: Initial commit This project was moved from master into 'usrpe31x' feature branch. To see the old commits, checkout the dev_prj_2018_r1 tag. --- projects/usrpe31x/Makefile | 17 ++ projects/usrpe31x/system_bd.tcl | 303 ++++++++++++++++++++++++++ projects/usrpe31x/system_constr.xdc | 157 ++++++++++++++ projects/usrpe31x/system_project.tcl | 16 ++ projects/usrpe31x/system_top.v | 309 +++++++++++++++++++++++++++ 5 files changed, 802 insertions(+) create mode 100644 projects/usrpe31x/Makefile create mode 100644 projects/usrpe31x/system_bd.tcl create mode 100644 projects/usrpe31x/system_constr.xdc create mode 100644 projects/usrpe31x/system_project.tcl create mode 100644 projects/usrpe31x/system_top.v diff --git a/projects/usrpe31x/Makefile b/projects/usrpe31x/Makefile new file mode 100644 index 000000000..cba7d715d --- /dev/null +++ b/projects/usrpe31x/Makefile @@ -0,0 +1,17 @@ +#################################################################################### +## Copyright 2018(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := usrpe31x + +M_DEPS += ../../library/xilinx/common/ad_iobuf.v +M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl + +LIB_DEPS += axi_ad9361 +LIB_DEPS += axi_dmac +LIB_DEPS += util_cpack +LIB_DEPS += util_tdd_sync +LIB_DEPS += util_upack + +include ../scripts/project-xilinx.mk diff --git a/projects/usrpe31x/system_bd.tcl b/projects/usrpe31x/system_bd.tcl new file mode 100644 index 000000000..733f5735f --- /dev/null +++ b/projects/usrpe31x/system_bd.tcl @@ -0,0 +1,303 @@ +# create board design +# default ports + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr +create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io + +create_bd_port -dir O spi0_csn_0 +create_bd_port -dir O spi0_csn_1 +create_bd_port -dir O spi0_csn_2 +create_bd_port -dir O spi0_clk +create_bd_port -dir O spi0_mosi +create_bd_port -dir I spi0_miso + +create_bd_port -dir I spi1_csn +create_bd_port -dir I spi1_clk +create_bd_port -dir I spi1_mosi +create_bd_port -dir O spi1_miso + +create_bd_port -dir I -from 63 -to 0 ps_gpio_i +create_bd_port -dir O -from 63 -to 0 ps_gpio_o +create_bd_port -dir O -from 63 -to 0 ps_gpio_t + +# interrupts + +create_bd_port -dir I -type intr ps_intr_00 +create_bd_port -dir I -type intr ps_intr_01 +create_bd_port -dir I -type intr ps_intr_02 +create_bd_port -dir I -type intr ps_intr_03 +create_bd_port -dir I -type intr ps_intr_04 +create_bd_port -dir I -type intr ps_intr_05 +create_bd_port -dir I -type intr ps_intr_06 +create_bd_port -dir I -type intr ps_intr_07 +create_bd_port -dir I -type intr ps_intr_08 +create_bd_port -dir I -type intr ps_intr_09 +create_bd_port -dir I -type intr ps_intr_10 +create_bd_port -dir I -type intr ps_intr_11 +create_bd_port -dir I -type intr ps_intr_12 +create_bd_port -dir I -type intr ps_intr_13 +create_bd_port -dir I -type intr ps_intr_14 +create_bd_port -dir I -type intr ps_intr_15 + +# instance: sys_ps7 + +ad_ip_instance processing_system7 sys_ps7 + +# ps7 settings + +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE "LVCMOS 1.8V" +ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE "LVCMOS 1.8V" +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO MIO +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_ENET0_IO "MIO 16 .. 27" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_RESET_IO "MIO 11" +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_ENET0_GRP_MDIO_IO "MIO 52 .. 53" +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_USB0_IO "MIO 28 .. 39" +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO "MIO 9" +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_SD0_IO "MIO 40 .. 45" +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_GRP_CD_IO "MIO 0" +ad_ip_parameter sys_ps7 CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ 50 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_SPI1_IO EMIO +ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART0_UART0_IO "MIO 14 .. 15" +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO "MIO 48 .. 49" +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO "MIO 46 .. 47" +ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE REVERSE + +# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks) + +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO Custom +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH "32 Bit" +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF 0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH "16 Bits" +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY "4096 MBits" +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_CWL 6 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RC 48.75 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN 35.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_T_FAW 40.0 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE 1 +ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE 1 + +ad_ip_instance xlconcat sys_concat_intc +ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16 + +ad_ip_instance proc_sys_reset sys_rstgen +ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1 + +# system reset/clock definitions + +ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0 +ad_connect sys_200m_clk sys_ps7/FCLK_CLK1 +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N + +# interface connections + +ad_connect ddr sys_ps7/DDR +ad_connect ps_gpio_i sys_ps7/GPIO_I +ad_connect ps_gpio_o sys_ps7/GPIO_O +ad_connect ps_gpio_t sys_ps7/GPIO_T +ad_connect fixed_io sys_ps7/FIXED_IO + +# spi connections + +ad_connect sys_ps7/SPI0_SS_O spi0_csn_0 +ad_connect sys_ps7/SPI0_SS1_O spi0_csn_1 +ad_connect sys_ps7/SPI0_SS2_O spi0_csn_2 +ad_connect sys_ps7/SPI0_SCLK_O spi0_clk +ad_connect sys_ps7/SPI0_MOSI_O spi0_mosi +ad_connect sys_ps7/SPI0_MISO_I spi0_miso +ad_connect sys_ps7/SPI0_SS_I VCC +ad_connect sys_ps7/SPI0_SCLK_I GND +ad_connect sys_ps7/SPI0_MOSI_I GND + +ad_connect sys_ps7/SPI1_SS_I spi1_csn +ad_connect sys_ps7/SPI1_SCLK_I spi1_clk +ad_connect sys_ps7/SPI1_MOSI_I spi1_mosi +ad_connect sys_ps7/SPI1_MISO_O spi1_miso +ad_connect sys_ps7/SPI1_MISO_I GND + +# interrupts + +ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P +ad_connect sys_concat_intc/In15 ps_intr_15 +ad_connect sys_concat_intc/In14 ps_intr_14 +ad_connect sys_concat_intc/In13 ps_intr_13 +ad_connect sys_concat_intc/In12 ps_intr_12 +ad_connect sys_concat_intc/In11 ps_intr_11 +ad_connect sys_concat_intc/In10 ps_intr_10 +ad_connect sys_concat_intc/In9 ps_intr_09 +ad_connect sys_concat_intc/In8 ps_intr_08 +ad_connect sys_concat_intc/In7 ps_intr_07 +ad_connect sys_concat_intc/In6 ps_intr_06 +ad_connect sys_concat_intc/In5 ps_intr_05 +ad_connect sys_concat_intc/In4 ps_intr_04 +ad_connect sys_concat_intc/In3 ps_intr_03 +ad_connect sys_concat_intc/In2 ps_intr_02 +ad_connect sys_concat_intc/In1 ps_intr_01 +ad_connect sys_concat_intc/In0 ps_intr_00 + +# ad9361 + +create_bd_port -dir I rx_clk_in +create_bd_port -dir I rx_frame_in +create_bd_port -dir I -from 11 -to 0 rx_data_in + +create_bd_port -dir O tx_clk_out +create_bd_port -dir O tx_frame_out +create_bd_port -dir O -from 11 -to 0 tx_data_out + +create_bd_port -dir O enable +create_bd_port -dir O txnrx +create_bd_port -dir I up_enable +create_bd_port -dir I up_txnrx + +# ad9361 core(s) + +ad_ip_instance axi_ad9361 axi_ad9361 +ad_ip_parameter axi_ad9361 CONFIG.ID 0 +ad_ip_parameter axi_ad9361 CONFIG.CMOS_OR_LVDS_N 1 +ad_ip_parameter axi_ad9361 CONFIG.ADC_INIT_DELAY 23 + +ad_ip_instance axi_dmac axi_ad9361_dac_dma +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 32 + +ad_ip_instance util_upack util_ad9361_dac_upack +ad_ip_parameter util_ad9361_dac_upack CONFIG.NUM_OF_CHANNELS 2 +ad_ip_parameter util_ad9361_dac_upack CONFIG.CHANNEL_DATA_WIDTH 16 + +ad_ip_instance axi_dmac axi_ad9361_adc_dma +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 32 + +ad_ip_instance util_cpack util_ad9361_adc_pack +ad_ip_parameter util_ad9361_adc_pack CONFIG.NUM_OF_CHANNELS 2 +ad_ip_parameter util_ad9361_adc_pack CONFIG.CHANNEL_DATA_WIDTH 16 + +# connections + +ad_connect rx_clk_in axi_ad9361/rx_clk_in +ad_connect rx_frame_in axi_ad9361/rx_frame_in +ad_connect rx_data_in axi_ad9361/rx_data_in +ad_connect tx_clk_out axi_ad9361/tx_clk_out +ad_connect tx_frame_out axi_ad9361/tx_frame_out +ad_connect tx_data_out axi_ad9361/tx_data_out +ad_connect enable axi_ad9361/enable +ad_connect txnrx axi_ad9361/txnrx +ad_connect up_enable axi_ad9361/up_enable +ad_connect up_txnrx axi_ad9361/up_txnrx + +ad_connect sys_200m_clk axi_ad9361/delay_clk +ad_connect axi_ad9361/l_clk axi_ad9361/clk + +ad_connect axi_ad9361/l_clk util_ad9361_adc_pack/adc_clk +ad_connect axi_ad9361/rst util_ad9361_adc_pack/adc_rst +ad_connect axi_ad9361/adc_enable_i0 util_ad9361_adc_pack/adc_enable_0 +ad_connect axi_ad9361/adc_valid_i0 util_ad9361_adc_pack/adc_valid_0 +ad_connect axi_ad9361/adc_data_i0 util_ad9361_adc_pack/adc_data_0 +ad_connect axi_ad9361/adc_enable_q0 util_ad9361_adc_pack/adc_enable_1 +ad_connect axi_ad9361/adc_valid_q0 util_ad9361_adc_pack/adc_valid_1 +ad_connect axi_ad9361/adc_data_q0 util_ad9361_adc_pack/adc_data_1 +ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk +ad_connect util_ad9361_adc_pack/adc_valid axi_ad9361_adc_dma/fifo_wr_en +ad_connect util_ad9361_adc_pack/adc_sync axi_ad9361_adc_dma/fifo_wr_sync +ad_connect util_ad9361_adc_pack/adc_data axi_ad9361_adc_dma/fifo_wr_din +ad_connect axi_ad9361_adc_dma/fifo_wr_overflow axi_ad9361/adc_dovf +ad_connect axi_ad9361/l_clk util_ad9361_dac_upack/dac_clk +ad_connect axi_ad9361/dac_enable_i0 util_ad9361_dac_upack/dac_enable_0 +ad_connect axi_ad9361/dac_valid_i0 util_ad9361_dac_upack/dac_valid_0 +ad_connect util_ad9361_dac_upack/dac_data_0 axi_ad9361/dac_data_i0 +ad_connect axi_ad9361/dac_enable_q0 util_ad9361_dac_upack/dac_enable_1 +ad_connect axi_ad9361/dac_valid_q0 util_ad9361_dac_upack/dac_valid_1 +ad_connect util_ad9361_dac_upack/dac_data_1 axi_ad9361/dac_data_q0 +ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/fifo_rd_clk +ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en +ad_connect axi_ad9361_dac_dma/fifo_rd_dout util_ad9361_dac_upack/dac_data +ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf +ad_connect axi_ad9361/dac_data_i1 GND +ad_connect axi_ad9361/dac_data_q1 GND + +# interconnects + +ad_cpu_interconnect 0x79020000 axi_ad9361 +ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma +ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi +ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi +ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn +ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq +ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq + +# tdd-sync + +ad_ip_instance util_tdd_sync util_ad9361_tdd_sync +ad_ip_parameter util_ad9361_tdd_sync CONFIG.TDD_SYNC_PERIOD 10000000 + +create_bd_port -dir I tdd_sync + +ad_connect tdd_sync util_ad9361_tdd_sync/sync_in +ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk +ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn +ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync +ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr + +# gpio + +create_bd_port -dir I -from 31 -to 0 pl_gpio_i +create_bd_port -dir O -from 31 -to 0 pl_gpio_o +create_bd_port -dir O -from 31 -to 0 pl_gpio_t + +ad_ip_instance axi_gpio axi_gpio +ad_ip_parameter axi_gpio CONFIG.C_GPIO_WIDTH 32 +ad_ip_parameter axi_gpio CONFIG.C_INTERRUPT_PRESENT 1 + +ad_connect pl_gpio_i axi_gpio/gpio_io_i +ad_connect pl_gpio_o axi_gpio/gpio_io_o +ad_connect pl_gpio_t axi_gpio/gpio_io_t + +ad_cpu_interconnect 0x41600000 axi_gpio +ad_cpu_interrupt ps-15 mb-15 axi_gpio/ip2intc_irpt + diff --git a/projects/usrpe31x/system_constr.xdc b/projects/usrpe31x/system_constr.xdc new file mode 100644 index 000000000..5c79afb70 --- /dev/null +++ b/projects/usrpe31x/system_constr.xdc @@ -0,0 +1,157 @@ + +# ad9361 (SWAP == 0x1) + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports rx_clk_in] +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS18} [get_ports rx_frame_in] +set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]] +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]] +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]] +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]] +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]] +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]] +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]] +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]] + +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS18} [get_ports tx_clk_out] +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18} [get_ports tx_frame_out] +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]] +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]] +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]] +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]] +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]] +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]] + +set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports enable] +set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18} [get_ports txnrx] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS18} [get_ports out_clk] + +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18} [get_ports gpio_resetb] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18} [get_ports gpio_sync] +set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc] +set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]] +set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]] +set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]] +set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]] +set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] +set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] +set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]] +set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]] +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]] +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]] +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]] +set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]] + +# not-connected? + +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[0]] +set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[1]] +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_rf[2]] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[3]] +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports gpio_rf[4]] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports gpio_rf[5]] +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18} [get_ports gpio_rf[6]] +set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports gpio_rf[7]] +set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS18} [get_ports gpio_rf[8]] + +# forwarded clocks (not-connected?) + +set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports gpio_tcxo_clk] +set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS18} [get_ports gpio_out_clk] + +# spi + +set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn] +set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_clk] +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports spi_mosi] +set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports spi_miso] + +create_clock -name rx_clk -period 16 [get_ports rx_clk_in] + +# rf filter selects + +set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[0]] +set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[1]] +set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[2]] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[0]] +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[1]] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[2]] +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1b[0]] +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1b[1]] +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1c[0]] +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1c[1]] +set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[0]] +set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[1]] +set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[2]] +set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2b[0]] +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2b[1]] +set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2c[0]] +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2c[1]] + +# rf enables + +set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports tx_enable_1a] +set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports tx_enable_2a] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports tx_enable_1b] +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports tx_enable_2b] + +# antennae selects + +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports txrx1_antsel_v1] +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports txrx1_antsel_v2] +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports txrx2_antsel_v1] +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports txrx2_antsel_v2] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports rx1_antsel_v1] +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports rx1_antsel_v2] +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports rx2_antsel_v1] +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports rx2_antsel_v2] + +# fancy stuff + +set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS18} [get_ports txrx1_tx_led] +set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports txrx1_rx_led] +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS18} [get_ports txrx2_tx_led] +set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports txrx2_rx_led] +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports rx1_rx_led] +set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports rx2_rx_led] + +# xtal tuning (ad5662) + +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_csn] +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_clk] +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_mosi] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS18} [get_ports tcxo_clk] + +# board power + +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports avr_csn] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports avr_clk] +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports avr_mosi] +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports avr_miso] +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports avr_irq] + +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports pwr_switch] + +# gps-sync + +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18} [get_ports pps_gps] +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports pps_ext] + +# board-gpio + +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]] +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]] + diff --git a/projects/usrpe31x/system_project.tcl b/projects/usrpe31x/system_project.tcl new file mode 100644 index 000000000..85b841a7d --- /dev/null +++ b/projects/usrpe31x/system_project.tcl @@ -0,0 +1,16 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg484-1" +adi_project_xilinx usrpe31x + +adi_project_files usrpe31x [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v"] + +adi_project_run usrpe31x +source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl + diff --git a/projects/usrpe31x/system_top.v b/projects/usrpe31x/system_top.v new file mode 100644 index 000000000..0b1d79c53 --- /dev/null +++ b/projects/usrpe31x/system_top.v @@ -0,0 +1,309 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + output enable, + output txnrx, + input out_clk, + + output gpio_resetb, + output gpio_sync, + output gpio_en_agc, + output [ 3:0] gpio_ctl, + input [ 7:0] gpio_status, + inout [ 8:0] gpio_rf, + output gpio_tcxo_clk, + output gpio_out_clk, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + output [ 2:0] tx_bandsel, + output [ 2:0] rx_bandsel_1, + output [ 1:0] rx_bandsel_1b, + output [ 1:0] rx_bandsel_1c, + output [ 2:0] rx_bandsel_2, + output [ 1:0] rx_bandsel_2b, + output [ 1:0] rx_bandsel_2c, + + output tx_enable_1a, + output tx_enable_2a, + output tx_enable_1b, + output tx_enable_2b, + + output txrx1_antsel_v1, + output txrx1_antsel_v2, + output txrx2_antsel_v1, + output txrx2_antsel_v2, + output rx1_antsel_v1, + output rx1_antsel_v2, + output rx2_antsel_v1, + output rx2_antsel_v2, + + output txrx1_tx_led, + output txrx1_rx_led, + output txrx2_tx_led, + output txrx2_rx_led, + output rx1_rx_led, + output rx2_rx_led, + + output tcxo_dac_csn, + output tcxo_dac_clk, + output tcxo_dac_mosi, + input tcxo_clk, + + input avr_csn, + input avr_clk, + input avr_mosi, + output avr_miso, + output avr_irq, + + input pwr_switch, + + input pps_gps, + input pps_ext, + + inout [ 5:0] gpio_bd); + + // internal signals + + wire pps_s; + wire [31:0] pl_gpio_i; + wire [31:0] pl_gpio_o; + wire [31:0] pl_gpio_t; + wire [63:0] ps_gpio_i; + wire [63:0] ps_gpio_o; + wire [63:0] ps_gpio_t; + + // assignments + + assign pps_s = pps_gps | pps_ext; + assign tcxo_dac_clk = spi_clk; + assign tcxo_dac_mosi = spi_mosi; + + // gpio-rf (pl) + + assign gpio_tcxo_clk = tcxo_clk; + assign gpio_out_clk = out_clk; + assign pl_gpio_i[31:9] = pl_gpio_o[31:9]; + + ad_iobuf #(.DATA_WIDTH(9)) i_iobuf_rf ( + .dio_t (pl_gpio_t[8:0]), + .dio_i (pl_gpio_o[8:0]), + .dio_o (pl_gpio_i[8:0]), + .dio_p (gpio_rf)); + + // gpio[63:56] - antennae selects + + assign ps_gpio_i[63:56] = ps_gpio_o[63:56]; + assign txrx1_antsel_v1 = ps_gpio_o[63]; + assign txrx1_antsel_v2 = ps_gpio_o[62]; + assign txrx2_antsel_v1 = ps_gpio_o[61]; + assign txrx2_antsel_v2 = ps_gpio_o[60]; + assign rx1_antsel_v1 = ps_gpio_o[59]; + assign rx1_antsel_v2 = ps_gpio_o[58]; + assign rx2_antsel_v1 = ps_gpio_o[57]; + assign rx2_antsel_v2 = ps_gpio_o[56]; + + // gpio[55:48] - antennae leds + + assign ps_gpio_i[55:49] = ps_gpio_o[55:49]; + assign txrx1_tx_led = ps_gpio_o[55]; + assign txrx1_rx_led = ps_gpio_o[54]; + assign txrx2_tx_led = ps_gpio_o[53]; + assign txrx2_rx_led = ps_gpio_o[52]; + assign rx1_rx_led = ps_gpio_o[51]; + assign rx2_rx_led = ps_gpio_o[50]; + + // gpio[48:32] - ad9361 + + assign ps_gpio_i[48:44] = ps_gpio_o[48:44]; + assign gpio_resetb = ps_gpio_o[46]; + assign gpio_sync = ps_gpio_o[45]; + assign gpio_en_agc = ps_gpio_o[44]; + + assign ps_gpio_i[43:40] = ps_gpio_o[43:40]; + assign gpio_ctl = ps_gpio_o[43:40]; + + assign ps_gpio_i[39:32] = gpio_status; + + // gpio[31:28] - tx_enable + + assign ps_gpio_i[31:28] = ps_gpio_o[31:28]; + + assign tx_enable_1a = ps_gpio_o[31]; + assign tx_enable_2a = ps_gpio_o[30]; + assign tx_enable_1b = ps_gpio_o[29]; + assign tx_enable_2b = ps_gpio_o[28]; + + // gpio[27:24] - tx_bandsel + + assign ps_gpio_i[27:24] = ps_gpio_o[27:24]; + + assign tx_bandsel = ps_gpio_o[26:24]; + + // gpio[23:16] - rx_bandsel(1) + + assign ps_gpio_i[23:16] = ps_gpio_o[23:16]; + + assign rx_bandsel_1 = ps_gpio_o[22:20]; + assign rx_bandsel_1b = ps_gpio_o[19:18]; + assign rx_bandsel_1c = ps_gpio_o[17:16]; + + // gpio[15:8] - rx_bandsel(2) + + assign ps_gpio_i[15:8] = ps_gpio_o[15:8]; + + assign rx_bandsel_2 = ps_gpio_o[14:12]; + assign rx_bandsel_2b = ps_gpio_o[11:10]; + assign rx_bandsel_2c = ps_gpio_o[9:8]; + + // gpio[7:0] - board stuff (+ pwr_switch, avr_irq) + + assign ps_gpio_i[7] = ps_gpio_o[7]; + assign avr_irq = ps_gpio_o[7]; + + assign ps_gpio_i[6] = pwr_switch; + + ad_iobuf #(.DATA_WIDTH(6)) i_iobuf_bd ( + .dio_t (ps_gpio_t[5:0]), + .dio_i (ps_gpio_o[5:0]), + .dio_o (ps_gpio_i[5:0]), + .dio_p (gpio_bd)); + + // instantiations + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .pl_gpio_i (pl_gpio_i), + .pl_gpio_o (pl_gpio_o), + .pl_gpio_t (pl_gpio_t), + .ps_gpio_i (ps_gpio_i), + .ps_gpio_o (ps_gpio_o), + .ps_gpio_t (ps_gpio_t), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .ps_intr_14 (1'b0), + .rx_clk_in (rx_clk_in), + .rx_data_in (rx_data_in), + .rx_frame_in (rx_frame_in), + .spi0_clk (spi_clk), + .spi0_csn_0 (spi_csn), + .spi0_csn_1 (tcxo_dac_csn), + .spi0_csn_2 (), + .spi0_miso (spi_miso), + .spi0_mosi (spi_mosi), + .spi1_clk (avr_clk), + .spi1_csn (avr_csn), + .spi1_miso (avr_miso), + .spi1_mosi (avr_mosi), + .tdd_sync (pps_s), + .tx_clk_out (tx_clk_out), + .tx_data_out (tx_data_out), + .tx_frame_out (tx_frame_out), + .txnrx (txnrx), + .up_enable (ps_gpio_o[47]), + .up_txnrx (ps_gpio_o[48])); + +endmodule + +// *************************************************************************** +// ***************************************************************************