projects: cn0540: coraz7s: Add XADC support
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended and 8 Differential Analog inputs tied to Xilinx's XADC. The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor the differential input, ADC driver, and buffer voltages. Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>main
Sergiu Cuciurean
István Csomortáni
parent
11822e2824
commit
da6d9da4f0
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@ -1,6 +1,13 @@
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adc_spi
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cn0540
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_mux
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux9
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux6
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux15
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux5
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux13
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create_bd_port -dir I adc_data_ready
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@ -99,11 +106,43 @@ ad_connect spi_adc/m_spi adc_spi
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ad_connect spi_clk spi_adc/spi_clk
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ad_connect axi_cn0540_dma/s_axis spi_adc/M_AXIS_SAMPLE
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# Xilinx's XADC
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ad_ip_instance xadc_wiz xadc_in
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ad_ip_parameter xadc_in CONFIG.XADC_STARUP_SELECTION channel_sequencer
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ad_ip_parameter xadc_in CONFIG.SEQUENCER_MODE Continuous
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VP_VN true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP5_VAUXN5 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP6_VAUXN6 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP9_VAUXN9 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP13_VAUXN13 true
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ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP15_VAUXN15 true
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ad_ip_parameter xadc_in CONFIG.ENABLE_VCCDDRO_ALARM false
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ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPAUX_ALARM false
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ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPINT_ALARM false
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ad_ip_parameter xadc_in CONFIG.EXTERNAL_MUX_CHANNEL VP_VN
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ad_ip_parameter xadc_in CONFIG.OT_ALARM false
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ad_ip_parameter xadc_in CONFIG.SINGLE_CHANNEL_SELECTION TEMPERATURE
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ad_ip_parameter xadc_in CONFIG.USER_TEMP_ALARM false
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ad_ip_parameter xadc_in CONFIG.VCCAUX_ALARM false
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ad_ip_parameter xadc_in CONFIG.VCCINT_ALARM false
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ad_connect xadc_in/Vp_Vn xadc_mux
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ad_connect xadc_in/Vaux1 xadc_vaux1
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ad_connect xadc_in/Vaux5 xadc_vaux5
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ad_connect xadc_in/Vaux6 xadc_vaux6
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ad_connect xadc_in/Vaux9 xadc_vaux9
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ad_connect xadc_in/Vaux13 xadc_vaux13
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ad_connect xadc_in/Vaux15 xadc_vaux15
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# AXI address definitions
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ad_cpu_interconnect 0x44a00000 spi_adc/axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_cn0540_dma
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ad_cpu_interconnect 0x44a40000 axi_iic_cn0540
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ad_cpu_interconnect 0x44a50000 xadc_in
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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ad_connect spi_clk axi_cn0540_dma/s_axis_aclk
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@ -38,3 +38,23 @@ create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*scl
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set_input_delay -clock [get_clocks spi_clk] [get_property PERIOD [get_clocks spi_clk]] \
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[get_ports -filter {NAME =~ "cn0540_spi_miso"}]
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## Dedicated Analog Inputs
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set_property -dict { PACKAGE_PIN K9 IOSTANDARD LVCMOS33 } [get_ports { cn0540_xadc_mux_p }]; #VP_0 Sch=xadc_v_p
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set_property -dict { PACKAGE_PIN L10 IOSTANDARD LVCMOS33 } [get_ports { cn0540_xadc_mux_n }]; #VN_0 Sch=xadc_v_n
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## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
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## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
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## WARNING: Do not use both sets of constraints at the same time!
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set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an0_p }]; #IO_L3P_T0_DQS_AD1P_35 Sch=ck_an_p[0]
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set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an0_n }]; #IO_L3N_T0_DQS_AD1N_35 Sch=ck_an_n[0]
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set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an1_p }]; #IO_L5P_T0_AD9P_35 Sch=ck_an_p[1]
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set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an1_n }]; #IO_L5N_T0_AD9N_35 Sch=ck_an_n[1]
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set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an2_p }]; #IO_L20P_T3_AD6P_35 Sch=ck_an_p[2]
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set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an2_n }]; #IO_L20N_T3_AD6N_35 Sch=ck_an_n[2]
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set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an3_p }]; #IO_L24P_T3_AD15P_35 Sch=ck_an_p[3]
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set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an3_n }]; #IO_L24N_T3_AD15N_35 Sch=ck_an_n[3]
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set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an4_p }]; #IO_L17P_T2_AD5P_35 Sch=ck_an_p[4]
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set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an4_n }]; #IO_L17N_T2_AD5N_35 Sch=ck_an_n[4]
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set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an5_p }]; #IO_L18P_T2_AD13P_35 Sch=ck_an_p[5]
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set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { cn0540_ck_an5_n }]; #IO_L18N_T2_AD13N_35 Sch=ck_an_n[5]
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@ -63,6 +63,21 @@ module system_top (
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inout [1:0] btn,
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inout [5:0] led,
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input cn0540_xadc_mux_p,
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input cn0540_xadc_mux_n,
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input cn0540_ck_an0_p,
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input cn0540_ck_an0_n,
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input cn0540_ck_an1_p,
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input cn0540_ck_an1_n,
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input cn0540_ck_an2_p,
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input cn0540_ck_an2_n,
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input cn0540_ck_an3_p,
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input cn0540_ck_an3_n,
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input cn0540_ck_an4_p,
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input cn0540_ck_an4_n,
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input cn0540_ck_an5_p,
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input cn0540_ck_an5_n,
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inout cn0540_scl,
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inout cn0540_sda,
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@ -176,7 +191,21 @@ module system_top (
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o());
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.spi1_sdo_o(),
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.xadc_mux_v_p (cn0540_xadc_mux_p),
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.xadc_mux_v_n (cn0540_xadc_mux_n),
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.xadc_vaux1_v_p (cn0540_ck_an0_p),
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.xadc_vaux1_v_n (cn0540_ck_an0_n),
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.xadc_vaux5_v_p (cn0540_ck_an4_p),
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.xadc_vaux5_v_n (cn0540_ck_an4_n),
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.xadc_vaux6_v_p (cn0540_ck_an2_p),
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.xadc_vaux6_v_n (cn0540_ck_an2_n),
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.xadc_vaux9_v_p (cn0540_ck_an1_p),
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.xadc_vaux9_v_n (cn0540_ck_an1_n),
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.xadc_vaux13_v_p (cn0540_ck_an5_p),
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.xadc_vaux13_v_n (cn0540_ck_an5_n),
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.xadc_vaux15_v_p (cn0540_ck_an3_p),
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.xadc_vaux15_v_n (cn0540_ck_an3_n));
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endmodule
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