From daf9e1744a446b43e7c537f8a2d1cfbfd9044d2d Mon Sep 17 00:00:00 2001 From: PIoandan <128376819+PIoandan@users.noreply.github.com> Date: Wed, 25 Oct 2023 17:15:23 +0300 Subject: [PATCH] pulsar_adc_pmdz: Add .txt file for constraints I changed the comments from system_constr.xdc file. Added pulsar_adc_pmdz_pmod.txt. Tests were done on the eval-ad7689-ebz and eval-ad7984-pmdz boards. Signed-off-by: Ioan-daniel Pop --- .../pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt | 9 +++++++++ projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc | 10 +++++----- 2 files changed, 14 insertions(+), 5 deletions(-) create mode 100644 projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt diff --git a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt new file mode 100644 index 000000000..38994e5ce --- /dev/null +++ b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_pmod.txt @@ -0,0 +1,9 @@ +Pin Port Schematic_name System_top_name IOSTANDARD Termination + +# pulsar_adc_pmdz + +4 PMOD_4 SCK pulsar_adc_spi_sclk LVCMOS33 #N/A +3 PMOD_3 SDO pulsar_adc_spi_sdi LVCMOS33 #N/A +2 PMOD_2 SDI pulsar_adc_spi_sdo LVCMOS33 #N/A +1 PMOD_1 CS pulsar_adc_spi_cs LVCMOS33 #N/A +7 PMOD_7 INT pulsar_adc_spi_pd LVCMOS33 #N/A diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc index 9cd15b372..0edac4ec5 100644 --- a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc +++ b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc @@ -4,12 +4,12 @@ ############################################################################### # ad40xx_fmc SPI interface -set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo] ; ## PMOD JA [2] -set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdi] ; ## PMOD JA [1] -set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sclk] ; ## PMOD JA [3] -set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_cs] ; ## PMOD JA [0] +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo] ; ## PMOD JA1_N +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdi] ; ## PMOD JA2_P +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sclk] ; ## PMOD JA2_N +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_cs] ; ## PMOD JA1_P -set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports pulsar_adc_spi_pd] ; ## PMOD JA [4] +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports pulsar_adc_spi_pd] ; ## PMOD JA3_P # rename auto-generated clock for SPIEngine to spi_clk - 160MHz # NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk