axi_ad9361: Fix Warning[Synth 8-2611]

In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.

library/axi_ad9361/axi_ad9361_tdd.v

@@ -83,7 +83,6 @@ module axi_ad9361_tdd (
 
   // internal signals
 
-  wire              rst;
   wire              tdd_enable_s;
   wire              tdd_secondary_s;
   wire    [ 7:0]    tdd_burst_count_s;