From db459d96e9153c19808c65f769eec66989d4bf58 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 28 Apr 2017 11:29:12 +0200 Subject: [PATCH] daq2: zc706: Increase DAC FIFO size Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is quite a limiting size for practical applications. Increase the size to 1MB to allow loading larger waveforms. In this configuration the DAC FIFO will use half of the available BRAM cells in the FPGA. This still leaves quite a few BRAMs available for user application logic added to the design. If a user design should run out of BRAMs nevertheless they can reduce the FIFO size, if not required by the application, to free up some cells. Signed-off-by: Lars-Peter Clausen --- projects/daq2/zc706/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/daq2/zc706/system_bd.tcl b/projects/daq2/zc706/system_bd.tcl index f958ed1b2..3e588e70f 100644 --- a/projects/daq2/zc706/system_bd.tcl +++ b/projects/daq2/zc706/system_bd.tcl @@ -3,7 +3,7 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl -p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 +p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 16 p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 create_bd_port -dir I -type rst sys_rst