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daq2: zc706: Increase DAC FIFO size 

Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.

In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-04-28 11:29:12 +02:00
parent edefb9df44
commit db459d96e9
1 changed files with 1 additions and 1 deletions
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projects/daq2/zc706/system_bd.tcl
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@ -3,7 +3,7 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl source $ad_hdl_dir/projects/common/xilinx/sys_dacfifo.tcl
p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10 p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 16
p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128 p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
create_bd_port -dir I -type rst sys_rst create_bd_port -dir I -type rst sys_rst