daq3: ZCU102: Remove Offload FIFO for ADC path.
DAC FIFO cannot be increased because of timing violationsmain
Adrian Costina
parent
9a74a40c49
commit
db51fb2829
|
|
@ -94,15 +94,19 @@ ad_connect axi_ad9152_core/dac_valid_0 axi_ad9152_upack/dac_valid_0
|
|||
ad_connect axi_ad9152_core/dac_enable_1 axi_ad9152_upack/dac_enable_1
|
||||
ad_connect axi_ad9152_core/dac_ddata_1 axi_ad9152_upack/dac_data_1
|
||||
ad_connect axi_ad9152_core/dac_valid_1 axi_ad9152_upack/dac_valid_1
|
||||
|
||||
if {$sys_zynq == 0 || $sys_zynq == 1} {
|
||||
ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk
|
||||
ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst
|
||||
ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk
|
||||
ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn
|
||||
ad_connect axi_ad9152_fifo/bypass GND
|
||||
}
|
||||
ad_connect util_daq3_xcvr/tx_out_clk_0 axi_ad9152_fifo/dac_clk
|
||||
ad_connect axi_ad9152_jesd_rstgen/peripheral_reset axi_ad9152_fifo/dac_rst
|
||||
ad_connect axi_ad9152_upack/dac_valid axi_ad9152_fifo/dac_valid
|
||||
ad_connect axi_ad9152_upack/dac_data axi_ad9152_fifo/dac_data
|
||||
ad_connect axi_ad9152_core/dac_dunf axi_ad9152_fifo/dac_dunf
|
||||
ad_connect sys_cpu_clk axi_ad9152_fifo/dma_clk
|
||||
ad_connect sys_cpu_reset axi_ad9152_fifo/dma_rst
|
||||
ad_connect sys_cpu_clk axi_ad9152_dma/m_axis_aclk
|
||||
ad_connect sys_cpu_resetn axi_ad9152_dma/m_src_axi_aresetn
|
||||
ad_connect axi_ad9152_fifo/dma_xfer_req axi_ad9152_dma/m_axis_xfer_req
|
||||
ad_connect axi_ad9152_fifo/dma_ready axi_ad9152_dma/m_axis_ready
|
||||
ad_connect axi_ad9152_fifo/dma_data axi_ad9152_dma/m_axis_data
|
||||
|
|
@ -123,18 +127,21 @@ ad_connect axi_ad9680_core/adc_data_0 axi_ad9680_cpack/adc_data_0
|
|||
ad_connect axi_ad9680_core/adc_enable_1 axi_ad9680_cpack/adc_enable_1
|
||||
ad_connect axi_ad9680_core/adc_valid_1 axi_ad9680_cpack/adc_valid_1
|
||||
ad_connect axi_ad9680_core/adc_data_1 axi_ad9680_cpack/adc_data_1
|
||||
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
|
||||
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
|
||||
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
|
||||
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
|
||||
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
|
||||
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
|
||||
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
|
||||
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
|
||||
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
|
||||
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
|
||||
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
|
||||
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
|
||||
|
||||
if {$sys_zynq == 0 || $sys_zynq == 1} {
|
||||
ad_connect util_daq3_xcvr/rx_out_clk_0 axi_ad9680_fifo/adc_clk
|
||||
ad_connect axi_ad9680_jesd_rstgen/peripheral_reset axi_ad9680_fifo/adc_rst
|
||||
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_fifo/adc_wr
|
||||
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_fifo/adc_wdata
|
||||
ad_connect sys_cpu_clk axi_ad9680_fifo/dma_clk
|
||||
ad_connect sys_cpu_clk axi_ad9680_dma/s_axis_aclk
|
||||
ad_connect sys_cpu_resetn axi_ad9680_dma/m_dest_axi_aresetn
|
||||
ad_connect axi_ad9680_fifo/dma_wr axi_ad9680_dma/s_axis_valid
|
||||
ad_connect axi_ad9680_fifo/dma_wdata axi_ad9680_dma/s_axis_data
|
||||
ad_connect axi_ad9680_fifo/dma_wready axi_ad9680_dma/s_axis_ready
|
||||
ad_connect axi_ad9680_fifo/dma_xfer_req axi_ad9680_dma/s_axis_xfer_req
|
||||
ad_connect axi_ad9680_core/adc_dovf axi_ad9680_fifo/adc_wovf
|
||||
}
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
|
|
@ -147,17 +154,15 @@ ad_cpu_interconnect 0x44A10000 axi_ad9680_core
|
|||
ad_cpu_interconnect 0x44AA0000 axi_ad9680_jesd
|
||||
ad_cpu_interconnect 0x7c400000 axi_ad9680_dma
|
||||
|
||||
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
|
||||
|
||||
# interconnect (mem/dac)
|
||||
|
||||
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9152_dma/m_src_axi
|
||||
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
|
||||
if {$sys_zynq == 0 || $sys_zynq == 1} {
|
||||
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_cpu_clk axi_ad9152_dma/m_src_axi
|
||||
ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
|
||||
ad_mem_hp2_interconnect sys_cpu_clk axi_ad9680_dma/m_dest_axi
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
|
||||
}
|
||||
|
||||
# interrupts
|
||||
|
||||
|
|
@ -165,6 +170,3 @@ ad_cpu_interrupt ps-10 mb-15 axi_ad9152_jesd/irq
|
|||
ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
|
||||
ad_cpu_interrupt ps-12 mb-13 axi_ad9152_dma/irq
|
||||
ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
|
||||
|
||||
ad_connect axi_ad9152_fifo/bypass GND
|
||||
|
||||
|
|
|
|||
|
|
@ -1,26 +1,74 @@
|
|||
|
||||
## FIFO depth is 8Mb - 500k samples
|
||||
set adc_fifo_name axi_ad9680_fifo
|
||||
set adc_fifo_address_width 17
|
||||
set adc_data_width 128
|
||||
set adc_dma_data_width 64
|
||||
|
||||
## FIFO depth is 8Mb - 500k samples
|
||||
set dac_fifo_name axi_ad9152_fifo
|
||||
set dac_fifo_address_width 16
|
||||
set dac_data_width 128
|
||||
set dac_dma_data_width 128
|
||||
|
||||
## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%
|
||||
## NOTE: With this configuration the #36Kb BRAM utilization is at ~28%
|
||||
|
||||
source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
|
||||
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
|
||||
source ../common/daq3_bd.tcl
|
||||
|
||||
create_bd_port -dir I dac_fifo_bypass
|
||||
|
||||
ad_ip_parameter axi_ad9152_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter axi_ad9680_xcvr CONFIG.XCVR_TYPE 2
|
||||
|
||||
ad_ip_parameter util_daq3_xcvr CONFIG.XCVR_TYPE 2
|
||||
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_FBDIV 20
|
||||
ad_ip_parameter util_daq3_xcvr CONFIG.QPLL_REFCLK_DIV 1
|
||||
|
||||
ad_ip_parameter axi_ad9152_dma CONFIG.FIFO_SIZE 32
|
||||
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_SRC 1
|
||||
ad_ip_parameter axi_ad9152_dma CONFIG.AXI_SLICE_DEST 1
|
||||
ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 1
|
||||
ad_ip_parameter axi_ad9152_dma CONFIG.MAX_BYTES_PER_BURST 256
|
||||
|
||||
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_TYPE_SRC 2
|
||||
ad_ip_parameter axi_ad9680_dma CONFIG.FIFO_SIZE 32
|
||||
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 128
|
||||
ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC 128
|
||||
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_SRC 1
|
||||
ad_ip_parameter axi_ad9680_dma CONFIG.AXI_SLICE_DEST 1
|
||||
ad_ip_parameter axi_ad9680_dma CONFIG.MAX_BYTES_PER_BURST 256
|
||||
|
||||
ad_ip_instance clk_wiz dma_clk_wiz
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 332.9
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer
|
||||
|
||||
ad_ip_instance proc_sys_reset sys_dma_rstgen
|
||||
|
||||
ad_connect sys_cpu_clk dma_clk_wiz/clk_in1
|
||||
ad_connect sys_cpu_resetn dma_clk_wiz/resetn
|
||||
|
||||
ad_connect sys_dma_clk dma_clk_wiz/clk_out1
|
||||
|
||||
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
|
||||
ad_connect sys_cpu_resetn sys_dma_rstgen/ext_reset_in
|
||||
|
||||
ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
|
||||
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
|
||||
|
||||
ad_connect sys_dma_clk axi_ad9152_fifo/dma_clk
|
||||
ad_connect sys_dma_reset axi_ad9152_fifo/dma_rst
|
||||
ad_connect sys_dma_clk axi_ad9152_dma/m_axis_aclk
|
||||
ad_connect sys_dma_resetn axi_ad9152_dma/m_src_axi_aresetn
|
||||
ad_connect axi_ad9152_fifo/bypass dac_fifo_bypass
|
||||
|
||||
ad_connect sys_dma_resetn axi_ad9680_dma/m_dest_axi_aresetn
|
||||
ad_connect axi_ad9680_dma/fifo_wr_clk util_daq3_xcvr/rx_out_clk_0
|
||||
ad_connect axi_ad9680_cpack/adc_data axi_ad9680_dma/fifo_wr_din
|
||||
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_dma/fifo_wr_en
|
||||
ad_connect axi_ad9680_cpack/adc_valid axi_ad9680_dma/fifo_wr_sync
|
||||
|
||||
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi
|
||||
ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1
|
||||
ad_mem_hp1_interconnect sys_dma_clk axi_ad9680_dma/m_dest_axi
|
||||
ad_mem_hp3_interconnect sys_dma_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_dma_clk axi_ad9152_dma/m_src_axi
|
||||
|
|
|
|||
|
|
@ -197,6 +197,7 @@ module system_top (
|
|||
.spi1_miso (1'd0),
|
||||
.spi1_mosi (),
|
||||
.spi1_sclk (),
|
||||
.dac_fifo_bypass(gpio_o[41]),
|
||||
.tx_data_0_n (tx_data_n[0]),
|
||||
.tx_data_0_p (tx_data_p[0]),
|
||||
.tx_data_1_n (tx_data_n[1]),
|
||||
|
|
|
|||
Loading…
Reference in New Issue