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pzsdr/ccfmc - loopback updates

main
Rejeesh Kutty 2016-09-22 11:17:42 -04:00
parent 2b6eb1d65e
commit dc6f7bbc4e
5 changed files with 382 additions and 589 deletions
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9
projects/pzsdr/ccfmc/Makefile
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@ -27,10 +27,9 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
M_DEPS += ../../../library/util_cpack/util_cpack.xpr M_DEPS += ../../../library/util_cpack/util_cpack.xpr
M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
M_DEPS += ../../../library/util_upack/util_upack.xpr M_DEPS += ../../../library/util_upack/util_upack.xpr
M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
@ -68,10 +67,9 @@ clean-all:clean
make -C ../../../library/axi_gpreg clean make -C ../../../library/axi_gpreg clean
make -C ../../../library/axi_hdmi_tx clean make -C ../../../library/axi_hdmi_tx clean
make -C ../../../library/axi_i2s_adi clean make -C ../../../library/axi_i2s_adi clean
make -C ../../../library/axi_jesd_gt clean
make -C ../../../library/axi_spdif_tx clean make -C ../../../library/axi_spdif_tx clean
make -C ../../../library/xilinx/axi_xcvrlb clean
make -C ../../../library/util_cpack clean make -C ../../../library/util_cpack clean
make -C ../../../library/util_gtlb clean
make -C ../../../library/util_tdd_sync clean make -C ../../../library/util_tdd_sync clean
make -C ../../../library/util_upack clean make -C ../../../library/util_upack clean
make -C ../../../library/util_wfifo clean make -C ../../../library/util_wfifo clean
@ -89,10 +87,9 @@ lib:
make -C ../../../library/axi_gpreg make -C ../../../library/axi_gpreg
make -C ../../../library/axi_hdmi_tx make -C ../../../library/axi_hdmi_tx
make -C ../../../library/axi_i2s_adi make -C ../../../library/axi_i2s_adi
make -C ../../../library/axi_jesd_gt
make -C ../../../library/axi_spdif_tx make -C ../../../library/axi_spdif_tx
make -C ../../../library/xilinx/axi_xcvrlb
make -C ../../../library/util_cpack make -C ../../../library/util_cpack
make -C ../../../library/util_gtlb
make -C ../../../library/util_tdd_sync make -C ../../../library/util_tdd_sync
make -C ../../../library/util_upack make -C ../../../library/util_upack
make -C ../../../library/util_wfifo make -C ../../../library/util_wfifo

37
projects/pzsdr/ccfmc/system_constr.xdc
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@ -100,12 +100,12 @@ set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## IO_L13P_T2_MRCC_13 (fmc_clk1_p) set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## IO_L13P_T2_MRCC_13 (fmc_clk1_p)
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## IO_L13N_T2_MRCC_13 (fmc_clk1_n) set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## IO_L13N_T2_MRCC_13 (fmc_clk1_n)
set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_0_p] ; ## MGTREFCLK0P_111 (fmc_gt_ref_clk_p) set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_p] ; ## MGTREFCLK0P_111 (fmc_gt_ref_clk_p)
set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_0_n] ; ## MGTREFCLK0N_111 (fmc_gt_ref_clk_n) set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_n] ; ## MGTREFCLK0N_111 (fmc_gt_ref_clk_n)
set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_0_p] ; ## MGTXTXP0_111 (fmc_gt_tx_p) set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_p[0]] ; ## MGTXTXP0_111 (fmc_gt_tx_p)
set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_0_n] ; ## MGTXTXN0_111 (fmc_gt_tx_n) set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_n[0]] ; ## MGTXTXN0_111 (fmc_gt_tx_n)
set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_0_p] ; ## MGTXRXP0_111 (fmc_gt_rx_p) set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_p[0]] ; ## MGTXRXP0_111 (fmc_gt_rx_p)
set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_0_n] ; ## MGTXRXN0_111 (fmc_gt_rx_n) set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_n[0]] ; ## MGTXRXN0_111 (fmc_gt_rx_n)
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_in_0] ; ## IO_25_13 (fmc_prstn) set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_in_0] ; ## IO_25_13 (fmc_prstn)
@ -180,20 +180,20 @@ set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[32
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## IO_L19N_T3_VREF_13 (fmc_la_n[33]) set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## IO_L19N_T3_VREF_13 (fmc_la_n[33])
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## IO_L21P_T3_DQS_13 (pmod0[0]) set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## IO_L21P_T3_DQS_13 (pmod0[0])
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_inout_0] ; ## IO_L21N_T3_DQS_13 (pmod0[1]) set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_in_1] ; ## IO_L21N_T3_DQS_13 (pmod0[1])
set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## IO_L22P_T3_13 (pmod0[2]) set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## IO_L22P_T3_13 (pmod0[2])
set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[36]] ; ## IO_L22N_T3_13 (pmod0[3]) set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[36]] ; ## IO_L22N_T3_13 (pmod0[3])
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[34]] ; ## IO_L23P_T3_13 (pmod0[4]) set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[34]] ; ## IO_L23P_T3_13 (pmod0[4])
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_inout_1] ; ## IO_L23N_T3_13 (pmod0[5]) + (TDD_SYNC) set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L23N_T3_13 (pmod0[5]) + (TDD_SYNC)
set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[35]] ; ## IO_L24P_T3_13 (pmod0[6]) set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[35]] ; ## IO_L24P_T3_13 (pmod0[6])
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[36]] ; ## IO_L24N_T3_13 (pmod0[7]) set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[36]] ; ## IO_L24N_T3_13 (pmod0[7])
set_property -dict {PACKAGE_PIN AA6} [get_ports gt_ref_clk_1_p] ; ## MGTREFCLK1P_111 (ad9517_gt_ref_clk_p) set_property -dict {PACKAGE_PIN AA6} [get_ports clk_2_p] ; ## MGTREFCLK1P_111 (ad9517_gt_ref_clk_p)
set_property -dict {PACKAGE_PIN AA5} [get_ports gt_ref_clk_1_n] ; ## MGTREFCLK1N_111 (ad9517_gt_ref_clk_n) set_property -dict {PACKAGE_PIN AA5} [get_ports clk_2_n] ; ## MGTREFCLK1N_111 (ad9517_gt_ref_clk_n)
set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_1_p] ; ## MGTXTXP1_111 (sfp_gt_tx_p) set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## MGTXTXP1_111 (sfp_gt_tx_p)
set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_1_n] ; ## MGTXTXN1_111 (sfp_gt_tx_n) set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## MGTXTXN1_111 (sfp_gt_tx_n)
set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_1_p] ; ## MGTXRXP1_111 (sfp_gt_rx_p) set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## MGTXRXP1_111 (sfp_gt_rx_p)
set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_1_n] ; ## MGTXRXN1_111 (sfp_gt_rx_n) set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## MGTXRXN1_111 (sfp_gt_rx_n)
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L1P_T0_34 (CAM_GPIO_0 ) set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L1P_T0_34 (CAM_GPIO_0 )
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L1N_T0_34 (CAM_GPIO_1 ) set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L1N_T0_34 (CAM_GPIO_1 )
@ -240,11 +240,8 @@ set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_inout
# clocks # clocks
create_clock -name ref_clk_0 -period 4.00 [get_ports gt_ref_clk_0_p] create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
create_clock -name ref_clk_1 -period 4.00 [get_ports gt_ref_clk_1_p] create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name tx_div_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK] create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
create_clock -name rx_div_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
create_clock -name tx_div_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
create_clock -name rx_div_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]

6
projects/pzsdr/ccfmc/system_project.tcl
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@ -1,6 +1,4 @@
source ../../scripts/adi_env.tcl source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl source $ad_hdl_dir/projects/scripts/adi_board.tcl
@ -14,10 +12,6 @@ adi_project_files ccfmc_pzsdr [list \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \ "$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ] "$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
adi_project_run ccfmc_pzsdr adi_project_run ccfmc_pzsdr

431
projects/pzsdr/ccfmc/system_top.v
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@ -39,254 +39,125 @@
module system_top ( module system_top (
ddr_addr, inout [14:0] ddr_addr,
ddr_ba, inout [ 2:0] ddr_ba,
ddr_cas_n, inout ddr_cas_n,
ddr_ck_n, inout ddr_ck_n,
ddr_ck_p, inout ddr_ck_p,
ddr_cke, inout ddr_cke,
ddr_cs_n, inout ddr_cs_n,
ddr_dm, inout [ 3:0] ddr_dm,
ddr_dq, inout [31:0] ddr_dq,
ddr_dqs_n, inout [ 3:0] ddr_dqs_n,
ddr_dqs_p, inout [ 3:0] ddr_dqs_p,
ddr_odt, inout ddr_odt,
ddr_ras_n, inout ddr_ras_n,
ddr_reset_n, inout ddr_reset_n,
ddr_we_n, inout ddr_we_n,
eth1_mdc, output eth1_mdc,
eth1_mdio, inout eth1_mdio,
eth1_rgmii_rxclk, input eth1_rgmii_rxclk,
eth1_rgmii_rxctl, input eth1_rgmii_rxctl,
eth1_rgmii_rxdata, input [ 3:0] eth1_rgmii_rxdata,
eth1_rgmii_txclk, output eth1_rgmii_txclk,
eth1_rgmii_txctl, output eth1_rgmii_txctl,
eth1_rgmii_txdata, output [ 3:0] eth1_rgmii_txdata,
fixed_io_ddr_vrn, inout fixed_io_ddr_vrn,
fixed_io_ddr_vrp, inout fixed_io_ddr_vrp,
fixed_io_mio, inout [53:0] fixed_io_mio,
fixed_io_ps_clk, inout fixed_io_ps_clk,
fixed_io_ps_porb, inout fixed_io_ps_porb,
fixed_io_ps_srstb, inout fixed_io_ps_srstb,
hdmi_out_clk, output hdmi_out_clk,
hdmi_vsync, output hdmi_vsync,
hdmi_hsync, output hdmi_hsync,
hdmi_data_e, output hdmi_data_e,
hdmi_data, output [15:0] hdmi_data,
hdmi_pd, output hdmi_pd,
hdmi_intn, input hdmi_intn,
spdif, output spdif,
spdif_in, input spdif_in,
i2s_mclk, output i2s_mclk,
i2s_bclk, output i2s_bclk,
i2s_lrclk, output i2s_lrclk,
i2s_sdata_out, output i2s_sdata_out,
i2s_sdata_in, input i2s_sdata_in,
iic_scl, inout iic_scl,
iic_sda, inout iic_sda,
gpio_bd, inout [11:0] gpio_bd,
fan_pwm, output fan_pwm,
fan_tach, input fan_tach,
clk_0_p, input clk_0_p,
clk_0_n, input clk_0_n,
clk_1_p, input clk_1_p,
clk_1_n, input clk_1_n,
gp_in_0, input clk_2_p,
gp_inout_0, input clk_2_n,
gp_inout_1, input gp_in_0,
gp_inout, input gp_in_1,
gp_out, inout [ 6:0] gp_inout,
gp_in, output [53:0] gp_out,
input [53:0] gp_in,
gt_ref_clk_0_p, input gt_ref_clk_p,
gt_ref_clk_0_n, input gt_ref_clk_n,
gt_ref_clk_1_p, output [ 1:0] gt_tx_p,
gt_ref_clk_1_n, output [ 1:0] gt_tx_n,
gt_tx_0_p, input [ 1:0] gt_rx_p,
gt_tx_0_n, input [ 1:0] gt_rx_n,
gt_rx_0_p,
gt_rx_0_n,
gt_tx_1_p,
gt_tx_1_n,
gt_rx_1_p,
gt_rx_1_n,
ad9517_csn, output ad9517_csn,
ad9517_clk, output ad9517_clk,
ad9517_mosi, output ad9517_mosi,
ad9517_miso, input ad9517_miso,
ad9517_pdn, inout ad9517_pdn,
ad9517_ref_sel, inout ad9517_ref_sel,
ad9517_ld, inout ad9517_ld,
ad9517_status, inout ad9517_status,
rx_clk_in_p, input rx_clk_in_p,
rx_clk_in_n, input rx_clk_in_n,
rx_frame_in_p, input rx_frame_in_p,
rx_frame_in_n, input rx_frame_in_n,
rx_data_in_p, input [ 5:0] rx_data_in_p,
rx_data_in_n, input [ 5:0] rx_data_in_n,
tx_clk_out_p, output tx_clk_out_p,
tx_clk_out_n, output tx_clk_out_n,
tx_frame_out_p, output tx_frame_out_p,
tx_frame_out_n, output tx_frame_out_n,
tx_data_out_p, output [ 5:0] tx_data_out_p,
tx_data_out_n, output [ 5:0] tx_data_out_n,
enable, output enable,
txnrx, output txnrx,
clk_out, input clk_out,
inout tdd_sync,
gpio_rf0, inout gpio_rf0,
gpio_rf1, inout gpio_rf1,
gpio_rf2, inout gpio_rf2,
gpio_rf3, inout gpio_rf3,
gpio_rfpwr_enable, inout gpio_rfpwr_enable,
gpio_clksel, inout gpio_clksel,
gpio_resetb, inout gpio_resetb,
gpio_sync, inout gpio_sync,
gpio_en_agc, inout gpio_en_agc,
gpio_ctl, inout [ 3:0] gpio_ctl,
gpio_status, inout [ 7:0] gpio_status,
spi_csn, output spi_csn,
spi_clk, output spi_clk,
spi_mosi, output spi_mosi,
spi_miso); input spi_miso);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
output eth1_mdc;
inout eth1_mdio;
input eth1_rgmii_rxclk;
input eth1_rgmii_rxctl;
input [ 3:0] eth1_rgmii_rxdata;
output eth1_rgmii_txclk;
output eth1_rgmii_txctl;
output [ 3:0] eth1_rgmii_txdata;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output hdmi_pd;
input hdmi_intn;
output spdif;
input spdif_in;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [11:0] gpio_bd;
output fan_pwm;
input fan_tach;
input clk_0_p;
input clk_0_n;
input clk_1_p;
input clk_1_n;
input gp_in_0;
inout gp_inout_0;
inout gp_inout_1;
inout [ 6:0] gp_inout;
output [53:0] gp_out;
input [53:0] gp_in;
input gt_ref_clk_0_p;
input gt_ref_clk_0_n;
input gt_ref_clk_1_p;
input gt_ref_clk_1_n;
output gt_tx_0_p;
output gt_tx_0_n;
input gt_rx_0_p;
input gt_rx_0_n;
output gt_tx_1_p;
output gt_tx_1_n;
input gt_rx_1_p;
input gt_rx_1_n;
output ad9517_csn;
output ad9517_clk;
output ad9517_mosi;
input ad9517_miso;
inout ad9517_pdn;
inout ad9517_ref_sel;
inout ad9517_ld;
inout ad9517_status;
input rx_clk_in_p;
input rx_clk_in_n;
input rx_frame_in_p;
input rx_frame_in_n;
input [ 5:0] rx_data_in_p;
input [ 5:0] rx_data_in_n;
output tx_clk_out_p;
output tx_clk_out_n;
output tx_frame_out_p;
output tx_frame_out_n;
output [ 5:0] tx_data_out_p;
output [ 5:0] tx_data_out_n;
output enable;
output txnrx;
input clk_out;
inout gpio_rf0;
inout gpio_rf1;
inout gpio_rf2;
inout gpio_rf3;
inout gpio_rfpwr_enable;
inout gpio_clksel;
inout gpio_resetb;
inout gpio_sync;
inout gpio_en_agc;
inout [ 3:0] gpio_ctl;
inout [ 7:0] gpio_status;
output spi_csn;
output spi_clk;
output spi_mosi;
input spi_miso;
// internal signals // internal signals
@ -296,11 +167,13 @@ module system_top (
wire spi_miso_s; wire spi_miso_s;
wire clk_0; wire clk_0;
wire clk_1; wire clk_1;
wire gt_ref_clk_0; wire clk_2;
wire gt_ref_clk_1; wire gt_ref_clk;
wire [63:0] gp_ioenb_s;
wire [63:0] gp_out_s; wire [63:0] gp_out_s;
wire [63:0] gp_in_s; wire [63:0] gp_in_s;
wire [63:0] gp_misc_out_s;
wire [63:0] gp_misc_in_s;
wire [63:0] gp_misc_ioenb_s;
wire [63:0] gpio_i; wire [63:0] gpio_i;
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
@ -320,6 +193,15 @@ module system_top (
assign ad9517_mosi = spi_mosi_s; assign ad9517_mosi = spi_mosi_s;
assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso); assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso);
assign gp_misc_in_s[63:10] = gp_misc_out_s[63:18];
assign gp_misc_in_s[9] = gp_in_1;
assign gp_misc_in_s[8] = gp_in_0;
assign gp_misc_in_s[7] = gp_misc_out_s[7];
assign gp_out[53:0] = gp_out_s[53:0];
assign gp_in_s[63:54] = gp_out_s[63:54];
assign gp_in_s[53:0] = gp_in[53:0];
// instantiations // instantiations
IBUFDS i_ibufds_clk_0 ( IBUFDS i_ibufds_clk_0 (
@ -332,48 +214,31 @@ module system_top (
.IB (clk_1_n), .IB (clk_1_n),
.O (clk_1)); .O (clk_1));
IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 ( IBUFDS_GTE2 i_ibufds_clk_2 (
.CEB (1'd0), .CEB (1'd0),
.I (gt_ref_clk_0_p), .I (clk_2_p),
.IB (gt_ref_clk_0_n), .IB (clk_2_n),
.O (gt_ref_clk_0), .O (clk_2),
.ODIV2 ()); .ODIV2 ());
IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 ( IBUFDS_GTE2 i_ibufds_gt_ref_clk (
.CEB (1'd0), .CEB (1'd0),
.I (gt_ref_clk_1_p), .I (gt_ref_clk_p),
.IB (gt_ref_clk_1_n), .IB (gt_ref_clk_n),
.O (gt_ref_clk_1), .O (gt_ref_clk),
.ODIV2 ()); .ODIV2 ());
assign gp_out[53:0] = gp_out_s[53:0]; ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_sfp (
assign gp_in_s[53:0] = gp_in[53:0]; .dio_t (gp_misc_ioenb_s[6:0]),
.dio_i (gp_misc_out_s[6:0]),
assign gp_in_s[63:63] = gp_in_0; .dio_o (gp_misc_in_s[6:0]),
assign gp_in_s[62:62] = gp_out_s[62];
assign gp_in_s[54:54] = gp_out_s[62] & gpio_tdd_sync_i;
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_61_55 (
.dio_t (gp_ioenb_s[61:55]),
.dio_i (gp_out_s[61:55]),
.dio_o (gp_in_s[61:55]),
.dio_p (gp_inout)); .dio_p (gp_inout));
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_0 ( ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
.dio_t (1'b0), .dio_t (tdd_sync_t),
.dio_i (gp_out_s[54]), .dio_i (tdd_sync_o),
.dio_o (), .dio_o (tdd_sync_i),
.dio_p (gp_inout_0)); .dio_p (tdd_sync));
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_1 (
.dio_t (gpio_tdd_sync_t),
.dio_i (gpio_tdd_sync_o),
.dio_o (gpio_tdd_sync_i),
.dio_p (gp_inout_1));
assign gpio_tdd_sync_t = gp_out_s[62] | tdd_sync_t;
assign gpio_tdd_sync_o = gp_out_s[62] | tdd_sync_o;
assign tdd_sync_i = ~gp_out_s[62] & gpio_tdd_sync_i;
ad_iobuf #(.DATA_WIDTH(25)) i_iobuf ( ad_iobuf #(.DATA_WIDTH(25)) i_iobuf (
.dio_t ({gpio_t[60:51], gpio_t[46:32]}), .dio_t ({gpio_t[60:51], gpio_t[46:32]}),
@ -404,6 +269,7 @@ module system_top (
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.clk_0 (clk_0), .clk_0 (clk_0),
.clk_1 (clk_1), .clk_1 (clk_1),
.clk_2 (clk_2),
.ddr_addr (ddr_addr), .ddr_addr (ddr_addr),
.ddr_ba (ddr_ba), .ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n), .ddr_cas_n (ddr_cas_n),
@ -445,23 +311,24 @@ module system_top (
.fixed_io_ps_srstb (fixed_io_ps_srstb), .fixed_io_ps_srstb (fixed_io_ps_srstb),
.gp_in_0 (gp_in_s[31:0]), .gp_in_0 (gp_in_s[31:0]),
.gp_in_1 (gp_in_s[63:32]), .gp_in_1 (gp_in_s[63:32]),
.gp_ioenb_0 (gp_ioenb_s[31:0]), .gp_in_2 (gp_misc_in_s[31:0]),
.gp_ioenb_1 (gp_ioenb_s[63:32]), .gp_in_3 (gp_misc_in_s[63:32]),
.gp_ioenb_0 (),
.gp_ioenb_1 (),
.gp_ioenb_2 (gp_misc_ioenb_s[31:0]),
.gp_ioenb_3 (gp_misc_ioenb_s[63:32]),
.gp_out_0 (gp_out_s[31:0]), .gp_out_0 (gp_out_s[31:0]),
.gp_out_1 (gp_out_s[63:32]), .gp_out_1 (gp_out_s[63:32]),
.gp_out_2 (gp_misc_out_s[31:0]),
.gp_out_3 (gp_misc_out_s[63:32]),
.gpio_i (gpio_i), .gpio_i (gpio_i),
.gpio_o (gpio_o), .gpio_o (gpio_o),
.gpio_t (gpio_t), .gpio_t (gpio_t),
.gt_ref_clk_0 (gt_ref_clk_0), .gt_ref_clk (gt_ref_clk),
.gt_ref_clk_1 (gt_ref_clk_1), .gt_rx_n (gt_rx_n),
.gt_rx_0_n (gt_rx_0_n), .gt_rx_p (gt_rx_p),
.gt_rx_0_p (gt_rx_0_p), .gt_tx_n (gt_tx_n),
.gt_rx_1_n (gt_rx_1_n), .gt_tx_p (gt_tx_p),
.gt_rx_1_p (gt_rx_1_p),
.gt_tx_0_n (gt_tx_0_n),
.gt_tx_0_p (gt_tx_0_p),
.gt_tx_1_n (gt_tx_1_n),
.gt_tx_1_p (gt_tx_1_p),
.hdmi_data (hdmi_data), .hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e), .hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync), .hdmi_hsync (hdmi_hsync),

130
projects/pzsdr/common/ccfmc_bd.tcl
View File

@ -155,127 +155,65 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
# un-used io (gt) # un-used io (gt)
set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt] set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb]
set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pzslb_gt set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pz_xcvrlb
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt
set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0] create_bd_port -dir I gt_ref_clk
set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1] create_bd_port -dir I -from 1 -to 0 gt_rx_p
create_bd_port -dir I -from 1 -to 0 gt_rx_n
create_bd_port -dir O -from 1 -to 0 gt_tx_p
create_bd_port -dir O -from 1 -to 0 gt_tx_n
ad_cpu_interconnect 0x44A60000 axi_pzslb_gt ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 ad_connect axi_pz_xcvrlb/ref_clk gt_ref_clk
ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi ad_connect axi_pz_xcvrlb/rx_p gt_rx_p
ad_connect axi_pz_xcvrlb/rx_n gt_rx_n
create_bd_port -dir I gt_ref_clk_0 ad_connect axi_pz_xcvrlb/tx_p gt_tx_p
create_bd_port -dir I gt_ref_clk_1 ad_connect axi_pz_xcvrlb/tx_n gt_tx_n
create_bd_port -dir I gt_rx_0_p
create_bd_port -dir I gt_rx_0_n
create_bd_port -dir O gt_tx_0_p
create_bd_port -dir O gt_tx_0_n
create_bd_port -dir I gt_rx_1_p
create_bd_port -dir I gt_rx_1_n
create_bd_port -dir O gt_tx_1_p
create_bd_port -dir O gt_tx_1_n
ad_connect sys_cpu_clk util_pzslb_gtlb_0/up_clk
ad_connect sys_cpu_resetn util_pzslb_gtlb_0/up_rstn
ad_connect util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk_0
ad_connect util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk_0
ad_connect util_pzslb_gtlb_0/rx_p gt_rx_0_p
ad_connect util_pzslb_gtlb_0/rx_n gt_rx_0_n
ad_connect util_pzslb_gtlb_0/tx_p gt_tx_0_p
ad_connect util_pzslb_gtlb_0/tx_n gt_tx_0_n
ad_connect sys_cpu_clk util_pzslb_gtlb_1/up_clk
ad_connect sys_cpu_resetn util_pzslb_gtlb_1/up_rstn
ad_connect util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk_0
ad_connect util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk_0
ad_connect util_pzslb_gtlb_1/rx_p gt_rx_1_p
ad_connect util_pzslb_gtlb_1/rx_n gt_rx_1_n
ad_connect util_pzslb_gtlb_1/tx_p gt_tx_1_p
ad_connect util_pzslb_gtlb_1/tx_n gt_tx_1_n
ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0
ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0
ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0
ad_connect axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
ad_connect axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
ad_connect axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
ad_connect axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
ad_connect axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0
# un-used io (regular) # un-used io (regular)
set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg] set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg set_property -dict [list CONFIG.NUM_OF_CLK_MONS {3}] $axi_gpreg
set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_5 {1}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg
set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg
set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
ad_cpu_interconnect 0x41200000 axi_gpreg
create_bd_port -dir I clk_0
create_bd_port -dir I clk_1
ad_connect clk_0 axi_gpreg/d_clk_0
ad_connect clk_1 axi_gpreg/d_clk_1
ad_connect gt_ref_clk_0 axi_gpreg/d_clk_2
ad_connect util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_3
ad_connect util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_4
ad_connect gt_ref_clk_1 axi_gpreg/d_clk_5
ad_connect util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_6
ad_connect util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_7
create_bd_port -dir I -from 31 -to 0 gp_in_0 create_bd_port -dir I -from 31 -to 0 gp_in_0
create_bd_port -dir I -from 31 -to 0 gp_in_1 create_bd_port -dir I -from 31 -to 0 gp_in_1
create_bd_port -dir I -from 31 -to 0 gp_in_2
create_bd_port -dir I -from 31 -to 0 gp_in_3
create_bd_port -dir O -from 31 -to 0 gp_out_0 create_bd_port -dir O -from 31 -to 0 gp_out_0
create_bd_port -dir O -from 31 -to 0 gp_out_1 create_bd_port -dir O -from 31 -to 0 gp_out_1
create_bd_port -dir O -from 31 -to 0 gp_out_2
create_bd_port -dir O -from 31 -to 0 gp_out_3
create_bd_port -dir O -from 31 -to 0 gp_ioenb_0 create_bd_port -dir O -from 31 -to 0 gp_ioenb_0
create_bd_port -dir O -from 31 -to 0 gp_ioenb_1 create_bd_port -dir O -from 31 -to 0 gp_ioenb_1
create_bd_port -dir O -from 31 -to 0 gp_ioenb_2
create_bd_port -dir O -from 31 -to 0 gp_ioenb_3
create_bd_port -dir I clk_0
create_bd_port -dir I clk_1
create_bd_port -dir I clk_2
ad_connect clk_0 axi_gpreg/d_clk_0
ad_connect clk_1 axi_gpreg/d_clk_1
ad_connect clk_2 axi_gpreg/d_clk_2
ad_connect gp_in_0 axi_gpreg/up_gp_in_0 ad_connect gp_in_0 axi_gpreg/up_gp_in_0
ad_connect gp_in_1 axi_gpreg/up_gp_in_1 ad_connect gp_in_1 axi_gpreg/up_gp_in_1
ad_connect gp_in_2 axi_gpreg/up_gp_in_2
ad_connect gp_in_3 axi_gpreg/up_gp_in_3
ad_connect gp_out_0 axi_gpreg/up_gp_out_0 ad_connect gp_out_0 axi_gpreg/up_gp_out_0
ad_connect gp_out_1 axi_gpreg/up_gp_out_1 ad_connect gp_out_1 axi_gpreg/up_gp_out_1
ad_connect gp_out_2 axi_gpreg/up_gp_out_2
ad_connect gp_out_3 axi_gpreg/up_gp_out_3
ad_connect gp_ioenb_0 axi_gpreg/up_gp_ioenb_0 ad_connect gp_ioenb_0 axi_gpreg/up_gp_ioenb_0
ad_connect gp_ioenb_1 axi_gpreg/up_gp_ioenb_1 ad_connect gp_ioenb_1 axi_gpreg/up_gp_ioenb_1
ad_connect axi_gpreg/up_gp_in_2 util_pzslb_gtlb_0/up_gp_out ad_connect gp_ioenb_2 axi_gpreg/up_gp_ioenb_2
ad_connect axi_gpreg/up_gp_out_2 util_pzslb_gtlb_0/up_gp_in ad_connect gp_ioenb_3 axi_gpreg/up_gp_ioenb_3
ad_connect axi_gpreg/up_gp_in_3 util_pzslb_gtlb_1/up_gp_out ad_cpu_interconnect 0x41200000 axi_gpreg
ad_connect axi_gpreg/up_gp_out_3 util_pzslb_gtlb_1/up_gp_in
## temporary (remove ila indirectly) ## temporary (remove ila indirectly)
delete_bd_objs [get_bd_cells ila_adc] delete_bd_objs [get_bd_cells ila_adc]
delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]