pzsdr/ccfmc - loopback updates
Rejeesh Kutty
parent
2b6eb1d65e
commit
dc6f7bbc4e
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@ -27,10 +27,9 @@ M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../../library/axi_gpreg/axi_gpreg.xpr
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M_DEPS += ../../../library/axi_hdmi_tx/axi_hdmi_tx.xpr
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M_DEPS += ../../../library/axi_i2s_adi/axi_i2s_adi.xpr
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M_DEPS += ../../../library/axi_jesd_gt/axi_jesd_gt.xpr
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M_DEPS += ../../../library/axi_spdif_tx/axi_spdif_tx.xpr
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M_DEPS += ../../../library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
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M_DEPS += ../../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../../library/util_gtlb/util_gtlb.xpr
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M_DEPS += ../../../library/util_tdd_sync/util_tdd_sync.xpr
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M_DEPS += ../../../library/util_upack/util_upack.xpr
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M_DEPS += ../../../library/util_wfifo/util_wfifo.xpr
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@ -68,10 +67,9 @@ clean-all:clean
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make -C ../../../library/axi_gpreg clean
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make -C ../../../library/axi_hdmi_tx clean
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make -C ../../../library/axi_i2s_adi clean
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make -C ../../../library/axi_jesd_gt clean
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make -C ../../../library/axi_spdif_tx clean
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make -C ../../../library/xilinx/axi_xcvrlb clean
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make -C ../../../library/util_cpack clean
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make -C ../../../library/util_gtlb clean
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make -C ../../../library/util_tdd_sync clean
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make -C ../../../library/util_upack clean
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make -C ../../../library/util_wfifo clean
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@ -89,10 +87,9 @@ lib:
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make -C ../../../library/axi_gpreg
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make -C ../../../library/axi_hdmi_tx
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make -C ../../../library/axi_i2s_adi
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make -C ../../../library/axi_jesd_gt
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make -C ../../../library/axi_spdif_tx
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make -C ../../../library/xilinx/axi_xcvrlb
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make -C ../../../library/util_cpack
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make -C ../../../library/util_gtlb
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make -C ../../../library/util_tdd_sync
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make -C ../../../library/util_upack
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make -C ../../../library/util_wfifo
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@ -100,12 +100,12 @@ set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_
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set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_p] ; ## IO_L13P_T2_MRCC_13 (fmc_clk1_p)
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set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports clk_1_n] ; ## IO_L13N_T2_MRCC_13 (fmc_clk1_n)
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set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_0_p] ; ## MGTREFCLK0P_111 (fmc_gt_ref_clk_p)
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set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_0_n] ; ## MGTREFCLK0N_111 (fmc_gt_ref_clk_n)
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set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_0_p] ; ## MGTXTXP0_111 (fmc_gt_tx_p)
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set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_0_n] ; ## MGTXTXN0_111 (fmc_gt_tx_n)
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set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_0_p] ; ## MGTXRXP0_111 (fmc_gt_rx_p)
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set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_0_n] ; ## MGTXRXN0_111 (fmc_gt_rx_n)
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set_property -dict {PACKAGE_PIN W6} [get_ports gt_ref_clk_p] ; ## MGTREFCLK0P_111 (fmc_gt_ref_clk_p)
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set_property -dict {PACKAGE_PIN W5} [get_ports gt_ref_clk_n] ; ## MGTREFCLK0N_111 (fmc_gt_ref_clk_n)
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set_property -dict {PACKAGE_PIN AF8} [get_ports gt_tx_p[0]] ; ## MGTXTXP0_111 (fmc_gt_tx_p)
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set_property -dict {PACKAGE_PIN AF7} [get_ports gt_tx_n[0]] ; ## MGTXTXN0_111 (fmc_gt_tx_n)
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set_property -dict {PACKAGE_PIN AD8} [get_ports gt_rx_p[0]] ; ## MGTXRXP0_111 (fmc_gt_rx_p)
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set_property -dict {PACKAGE_PIN AD7} [get_ports gt_rx_n[0]] ; ## MGTXRXN0_111 (fmc_gt_rx_n)
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set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports gp_in_0] ; ## IO_25_13 (fmc_prstn)
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@ -180,20 +180,20 @@ set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports gp_in[32
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set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS25} [get_ports gp_in[33]] ; ## IO_L19N_T3_VREF_13 (fmc_la_n[33])
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set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS25} [get_ports gp_out[34]] ; ## IO_L21P_T3_DQS_13 (pmod0[0])
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set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_inout_0] ; ## IO_L21N_T3_DQS_13 (pmod0[1])
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set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports gp_in_1] ; ## IO_L21N_T3_DQS_13 (pmod0[1])
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS25} [get_ports gp_out[35]] ; ## IO_L22P_T3_13 (pmod0[2])
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set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS25} [get_ports gp_out[36]] ; ## IO_L22N_T3_13 (pmod0[3])
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set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports gp_in[34]] ; ## IO_L23P_T3_13 (pmod0[4])
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports gp_inout_1] ; ## IO_L23N_T3_13 (pmod0[5]) + (TDD_SYNC)
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L23N_T3_13 (pmod0[5]) + (TDD_SYNC)
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set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports gp_in[35]] ; ## IO_L24P_T3_13 (pmod0[6])
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set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports gp_in[36]] ; ## IO_L24N_T3_13 (pmod0[7])
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set_property -dict {PACKAGE_PIN AA6} [get_ports gt_ref_clk_1_p] ; ## MGTREFCLK1P_111 (ad9517_gt_ref_clk_p)
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set_property -dict {PACKAGE_PIN AA5} [get_ports gt_ref_clk_1_n] ; ## MGTREFCLK1N_111 (ad9517_gt_ref_clk_n)
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set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_1_p] ; ## MGTXTXP1_111 (sfp_gt_tx_p)
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set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_1_n] ; ## MGTXTXN1_111 (sfp_gt_tx_n)
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set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_1_p] ; ## MGTXRXP1_111 (sfp_gt_rx_p)
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set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_1_n] ; ## MGTXRXN1_111 (sfp_gt_rx_n)
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set_property -dict {PACKAGE_PIN AA6} [get_ports clk_2_p] ; ## MGTREFCLK1P_111 (ad9517_gt_ref_clk_p)
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set_property -dict {PACKAGE_PIN AA5} [get_ports clk_2_n] ; ## MGTREFCLK1N_111 (ad9517_gt_ref_clk_n)
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set_property -dict {PACKAGE_PIN AF4} [get_ports gt_tx_p[1]] ; ## MGTXTXP1_111 (sfp_gt_tx_p)
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set_property -dict {PACKAGE_PIN AF3} [get_ports gt_tx_n[1]] ; ## MGTXTXN1_111 (sfp_gt_tx_n)
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set_property -dict {PACKAGE_PIN AE6} [get_ports gt_rx_p[1]] ; ## MGTXRXP1_111 (sfp_gt_rx_p)
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set_property -dict {PACKAGE_PIN AE5} [get_ports gt_rx_n[1]] ; ## MGTXRXN1_111 (sfp_gt_rx_n)
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set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports gp_in[37]] ; ## IO_L1P_T0_34 (CAM_GPIO_0 )
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set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports gp_in[38]] ; ## IO_L1N_T0_34 (CAM_GPIO_1 )
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@ -240,11 +240,8 @@ set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gp_inout
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# clocks
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create_clock -name ref_clk_0 -period 4.00 [get_ports gt_ref_clk_0_p]
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create_clock -name ref_clk_1 -period 4.00 [get_ports gt_ref_clk_1_p]
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create_clock -name tx_div_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name tx_div_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
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create_clock -name rx_div_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pzslb_gt/inst/g_lane_1[1].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
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create_clock -name ref_clk -period 4.00 [get_ports gt_ref_clk_p]
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create_clock -name xcvr_clk_0 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[0].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
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create_clock -name xcvr_clk_1 -period 8.00 [get_pins i_system_wrapper/system_i/axi_pz_xcvrlb/inst/g_lanes[1].i_xcvrlb_1/i_xch/i_gtxe2_channel/RXOUTCLK]
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@ -1,6 +1,4 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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@ -14,10 +12,6 @@ adi_project_files ccfmc_pzsdr [list \
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"$ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc" \
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"$ad_hdl_dir/projects/common/pzsdr/pzsdr_lvds_system_constr.xdc" ]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files $ad_hdl_dir/projects/common/pzsdr/pzsdr_bd_system_constr.xdc]
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set_property PROCESSING_ORDER EARLY [get_files system_constr.xdc]
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adi_project_run ccfmc_pzsdr
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@ -39,254 +39,125 @@
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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eth1_mdc,
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eth1_mdio,
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eth1_rgmii_rxclk,
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eth1_rgmii_rxctl,
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eth1_rgmii_rxdata,
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eth1_rgmii_txclk,
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eth1_rgmii_txctl,
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eth1_rgmii_txdata,
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output eth1_mdc,
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inout eth1_mdio,
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input eth1_rgmii_rxclk,
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input eth1_rgmii_rxctl,
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input [ 3:0] eth1_rgmii_rxdata,
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output eth1_rgmii_txclk,
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output eth1_rgmii_txctl,
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output [ 3:0] eth1_rgmii_txdata,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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hdmi_pd,
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hdmi_intn,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [15:0] hdmi_data,
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output hdmi_pd,
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input hdmi_intn,
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spdif,
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spdif_in,
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output spdif,
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input spdif_in,
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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output i2s_mclk,
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output i2s_bclk,
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output i2s_lrclk,
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output i2s_sdata_out,
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input i2s_sdata_in,
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iic_scl,
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iic_sda,
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inout iic_scl,
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inout iic_sda,
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gpio_bd,
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inout [11:0] gpio_bd,
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fan_pwm,
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fan_tach,
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output fan_pwm,
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input fan_tach,
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clk_0_p,
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clk_0_n,
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clk_1_p,
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clk_1_n,
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gp_in_0,
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gp_inout_0,
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gp_inout_1,
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gp_inout,
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gp_out,
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gp_in,
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input clk_0_p,
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input clk_0_n,
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input clk_1_p,
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input clk_1_n,
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input clk_2_p,
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input clk_2_n,
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input gp_in_0,
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input gp_in_1,
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inout [ 6:0] gp_inout,
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output [53:0] gp_out,
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input [53:0] gp_in,
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gt_ref_clk_0_p,
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gt_ref_clk_0_n,
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gt_ref_clk_1_p,
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gt_ref_clk_1_n,
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gt_tx_0_p,
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gt_tx_0_n,
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gt_rx_0_p,
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gt_rx_0_n,
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gt_tx_1_p,
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gt_tx_1_n,
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gt_rx_1_p,
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gt_rx_1_n,
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input gt_ref_clk_p,
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input gt_ref_clk_n,
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output [ 1:0] gt_tx_p,
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output [ 1:0] gt_tx_n,
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input [ 1:0] gt_rx_p,
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input [ 1:0] gt_rx_n,
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ad9517_csn,
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ad9517_clk,
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ad9517_mosi,
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ad9517_miso,
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ad9517_pdn,
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ad9517_ref_sel,
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ad9517_ld,
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ad9517_status,
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output ad9517_csn,
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output ad9517_clk,
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output ad9517_mosi,
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input ad9517_miso,
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inout ad9517_pdn,
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inout ad9517_ref_sel,
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inout ad9517_ld,
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inout ad9517_status,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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enable,
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txnrx,
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clk_out,
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output enable,
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output txnrx,
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input clk_out,
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inout tdd_sync,
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gpio_rf0,
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gpio_rf1,
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gpio_rf2,
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gpio_rf3,
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gpio_rfpwr_enable,
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gpio_clksel,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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inout gpio_rf0,
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inout gpio_rf1,
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inout gpio_rf2,
|
||||
inout gpio_rf3,
|
||||
inout gpio_rfpwr_enable,
|
||||
inout gpio_clksel,
|
||||
inout gpio_resetb,
|
||||
inout gpio_sync,
|
||||
inout gpio_en_agc,
|
||||
inout [ 3:0] gpio_ctl,
|
||||
inout [ 7:0] gpio_status,
|
||||
|
||||
spi_csn,
|
||||
spi_clk,
|
||||
spi_mosi,
|
||||
spi_miso);
|
||||
|
||||
|
||||
inout [14:0] ddr_addr;
|
||||
inout [ 2:0] ddr_ba;
|
||||
inout ddr_cas_n;
|
||||
inout ddr_ck_n;
|
||||
inout ddr_ck_p;
|
||||
inout ddr_cke;
|
||||
inout ddr_cs_n;
|
||||
inout [ 3:0] ddr_dm;
|
||||
inout [31:0] ddr_dq;
|
||||
inout [ 3:0] ddr_dqs_n;
|
||||
inout [ 3:0] ddr_dqs_p;
|
||||
inout ddr_odt;
|
||||
inout ddr_ras_n;
|
||||
inout ddr_reset_n;
|
||||
inout ddr_we_n;
|
||||
|
||||
output eth1_mdc;
|
||||
inout eth1_mdio;
|
||||
input eth1_rgmii_rxclk;
|
||||
input eth1_rgmii_rxctl;
|
||||
input [ 3:0] eth1_rgmii_rxdata;
|
||||
output eth1_rgmii_txclk;
|
||||
output eth1_rgmii_txctl;
|
||||
output [ 3:0] eth1_rgmii_txdata;
|
||||
|
||||
inout fixed_io_ddr_vrn;
|
||||
inout fixed_io_ddr_vrp;
|
||||
inout [53:0] fixed_io_mio;
|
||||
inout fixed_io_ps_clk;
|
||||
inout fixed_io_ps_porb;
|
||||
inout fixed_io_ps_srstb;
|
||||
|
||||
output hdmi_out_clk;
|
||||
output hdmi_vsync;
|
||||
output hdmi_hsync;
|
||||
output hdmi_data_e;
|
||||
output [15:0] hdmi_data;
|
||||
output hdmi_pd;
|
||||
input hdmi_intn;
|
||||
|
||||
output spdif;
|
||||
input spdif_in;
|
||||
|
||||
output i2s_mclk;
|
||||
output i2s_bclk;
|
||||
output i2s_lrclk;
|
||||
output i2s_sdata_out;
|
||||
input i2s_sdata_in;
|
||||
|
||||
inout iic_scl;
|
||||
inout iic_sda;
|
||||
|
||||
inout [11:0] gpio_bd;
|
||||
|
||||
output fan_pwm;
|
||||
input fan_tach;
|
||||
|
||||
input clk_0_p;
|
||||
input clk_0_n;
|
||||
input clk_1_p;
|
||||
input clk_1_n;
|
||||
input gp_in_0;
|
||||
inout gp_inout_0;
|
||||
inout gp_inout_1;
|
||||
inout [ 6:0] gp_inout;
|
||||
output [53:0] gp_out;
|
||||
input [53:0] gp_in;
|
||||
|
||||
input gt_ref_clk_0_p;
|
||||
input gt_ref_clk_0_n;
|
||||
input gt_ref_clk_1_p;
|
||||
input gt_ref_clk_1_n;
|
||||
output gt_tx_0_p;
|
||||
output gt_tx_0_n;
|
||||
input gt_rx_0_p;
|
||||
input gt_rx_0_n;
|
||||
output gt_tx_1_p;
|
||||
output gt_tx_1_n;
|
||||
input gt_rx_1_p;
|
||||
input gt_rx_1_n;
|
||||
|
||||
output ad9517_csn;
|
||||
output ad9517_clk;
|
||||
output ad9517_mosi;
|
||||
input ad9517_miso;
|
||||
inout ad9517_pdn;
|
||||
inout ad9517_ref_sel;
|
||||
inout ad9517_ld;
|
||||
inout ad9517_status;
|
||||
|
||||
input rx_clk_in_p;
|
||||
input rx_clk_in_n;
|
||||
input rx_frame_in_p;
|
||||
input rx_frame_in_n;
|
||||
input [ 5:0] rx_data_in_p;
|
||||
input [ 5:0] rx_data_in_n;
|
||||
output tx_clk_out_p;
|
||||
output tx_clk_out_n;
|
||||
output tx_frame_out_p;
|
||||
output tx_frame_out_n;
|
||||
output [ 5:0] tx_data_out_p;
|
||||
output [ 5:0] tx_data_out_n;
|
||||
|
||||
output enable;
|
||||
output txnrx;
|
||||
input clk_out;
|
||||
|
||||
inout gpio_rf0;
|
||||
inout gpio_rf1;
|
||||
inout gpio_rf2;
|
||||
inout gpio_rf3;
|
||||
inout gpio_rfpwr_enable;
|
||||
inout gpio_clksel;
|
||||
inout gpio_resetb;
|
||||
inout gpio_sync;
|
||||
inout gpio_en_agc;
|
||||
inout [ 3:0] gpio_ctl;
|
||||
inout [ 7:0] gpio_status;
|
||||
|
||||
output spi_csn;
|
||||
output spi_clk;
|
||||
output spi_mosi;
|
||||
input spi_miso;
|
||||
output spi_csn,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso);
|
||||
|
||||
// internal signals
|
||||
|
||||
|
|
@ -296,11 +167,13 @@ module system_top (
|
|||
wire spi_miso_s;
|
||||
wire clk_0;
|
||||
wire clk_1;
|
||||
wire gt_ref_clk_0;
|
||||
wire gt_ref_clk_1;
|
||||
wire [63:0] gp_ioenb_s;
|
||||
wire clk_2;
|
||||
wire gt_ref_clk;
|
||||
wire [63:0] gp_out_s;
|
||||
wire [63:0] gp_in_s;
|
||||
wire [63:0] gp_misc_out_s;
|
||||
wire [63:0] gp_misc_in_s;
|
||||
wire [63:0] gp_misc_ioenb_s;
|
||||
wire [63:0] gpio_i;
|
||||
wire [63:0] gpio_o;
|
||||
wire [63:0] gpio_t;
|
||||
|
|
@ -320,6 +193,15 @@ module system_top (
|
|||
assign ad9517_mosi = spi_mosi_s;
|
||||
assign spi_miso_s = (~spi_csn_s[0] & spi_miso) | (~spi_csn_s[1] & ad9517_miso);
|
||||
|
||||
assign gp_misc_in_s[63:10] = gp_misc_out_s[63:18];
|
||||
assign gp_misc_in_s[9] = gp_in_1;
|
||||
assign gp_misc_in_s[8] = gp_in_0;
|
||||
assign gp_misc_in_s[7] = gp_misc_out_s[7];
|
||||
|
||||
assign gp_out[53:0] = gp_out_s[53:0];
|
||||
assign gp_in_s[63:54] = gp_out_s[63:54];
|
||||
assign gp_in_s[53:0] = gp_in[53:0];
|
||||
|
||||
// instantiations
|
||||
|
||||
IBUFDS i_ibufds_clk_0 (
|
||||
|
|
@ -332,48 +214,31 @@ module system_top (
|
|||
.IB (clk_1_n),
|
||||
.O (clk_1));
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_gt_ref_clk_0 (
|
||||
IBUFDS_GTE2 i_ibufds_clk_2 (
|
||||
.CEB (1'd0),
|
||||
.I (gt_ref_clk_0_p),
|
||||
.IB (gt_ref_clk_0_n),
|
||||
.O (gt_ref_clk_0),
|
||||
.I (clk_2_p),
|
||||
.IB (clk_2_n),
|
||||
.O (clk_2),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS_GTE2 i_ibufds_gt_ref_clk_1 (
|
||||
IBUFDS_GTE2 i_ibufds_gt_ref_clk (
|
||||
.CEB (1'd0),
|
||||
.I (gt_ref_clk_1_p),
|
||||
.IB (gt_ref_clk_1_n),
|
||||
.O (gt_ref_clk_1),
|
||||
.I (gt_ref_clk_p),
|
||||
.IB (gt_ref_clk_n),
|
||||
.O (gt_ref_clk),
|
||||
.ODIV2 ());
|
||||
|
||||
assign gp_out[53:0] = gp_out_s[53:0];
|
||||
assign gp_in_s[53:0] = gp_in[53:0];
|
||||
|
||||
assign gp_in_s[63:63] = gp_in_0;
|
||||
assign gp_in_s[62:62] = gp_out_s[62];
|
||||
assign gp_in_s[54:54] = gp_out_s[62] & gpio_tdd_sync_i;
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_61_55 (
|
||||
.dio_t (gp_ioenb_s[61:55]),
|
||||
.dio_i (gp_out_s[61:55]),
|
||||
.dio_o (gp_in_s[61:55]),
|
||||
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_sfp (
|
||||
.dio_t (gp_misc_ioenb_s[6:0]),
|
||||
.dio_i (gp_misc_out_s[6:0]),
|
||||
.dio_o (gp_misc_in_s[6:0]),
|
||||
.dio_p (gp_inout));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_0 (
|
||||
.dio_t (1'b0),
|
||||
.dio_i (gp_out_s[54]),
|
||||
.dio_o (),
|
||||
.dio_p (gp_inout_0));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_54_1 (
|
||||
.dio_t (gpio_tdd_sync_t),
|
||||
.dio_i (gpio_tdd_sync_o),
|
||||
.dio_o (gpio_tdd_sync_i),
|
||||
.dio_p (gp_inout_1));
|
||||
|
||||
assign gpio_tdd_sync_t = gp_out_s[62] | tdd_sync_t;
|
||||
assign gpio_tdd_sync_o = gp_out_s[62] | tdd_sync_o;
|
||||
assign tdd_sync_i = ~gp_out_s[62] & gpio_tdd_sync_i;
|
||||
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
|
||||
.dio_t (tdd_sync_t),
|
||||
.dio_i (tdd_sync_o),
|
||||
.dio_o (tdd_sync_i),
|
||||
.dio_p (tdd_sync));
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(25)) i_iobuf (
|
||||
.dio_t ({gpio_t[60:51], gpio_t[46:32]}),
|
||||
|
|
@ -404,6 +269,7 @@ module system_top (
|
|||
system_wrapper i_system_wrapper (
|
||||
.clk_0 (clk_0),
|
||||
.clk_1 (clk_1),
|
||||
.clk_2 (clk_2),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
|
|
@ -445,23 +311,24 @@ module system_top (
|
|||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gp_in_0 (gp_in_s[31:0]),
|
||||
.gp_in_1 (gp_in_s[63:32]),
|
||||
.gp_ioenb_0 (gp_ioenb_s[31:0]),
|
||||
.gp_ioenb_1 (gp_ioenb_s[63:32]),
|
||||
.gp_in_2 (gp_misc_in_s[31:0]),
|
||||
.gp_in_3 (gp_misc_in_s[63:32]),
|
||||
.gp_ioenb_0 (),
|
||||
.gp_ioenb_1 (),
|
||||
.gp_ioenb_2 (gp_misc_ioenb_s[31:0]),
|
||||
.gp_ioenb_3 (gp_misc_ioenb_s[63:32]),
|
||||
.gp_out_0 (gp_out_s[31:0]),
|
||||
.gp_out_1 (gp_out_s[63:32]),
|
||||
.gp_out_2 (gp_misc_out_s[31:0]),
|
||||
.gp_out_3 (gp_misc_out_s[63:32]),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.gt_ref_clk_0 (gt_ref_clk_0),
|
||||
.gt_ref_clk_1 (gt_ref_clk_1),
|
||||
.gt_rx_0_n (gt_rx_0_n),
|
||||
.gt_rx_0_p (gt_rx_0_p),
|
||||
.gt_rx_1_n (gt_rx_1_n),
|
||||
.gt_rx_1_p (gt_rx_1_p),
|
||||
.gt_tx_0_n (gt_tx_0_n),
|
||||
.gt_tx_0_p (gt_tx_0_p),
|
||||
.gt_tx_1_n (gt_tx_1_n),
|
||||
.gt_tx_1_p (gt_tx_1_p),
|
||||
.gt_ref_clk (gt_ref_clk),
|
||||
.gt_rx_n (gt_rx_n),
|
||||
.gt_rx_p (gt_rx_p),
|
||||
.gt_tx_n (gt_tx_n),
|
||||
.gt_tx_p (gt_tx_p),
|
||||
.hdmi_data (hdmi_data),
|
||||
.hdmi_data_e (hdmi_data_e),
|
||||
.hdmi_hsync (hdmi_hsync),
|
||||
|
|
|
|||
|
|
@ -155,127 +155,65 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
|
|||
|
||||
# un-used io (gt)
|
||||
|
||||
set axi_pzslb_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_pzslb_gt]
|
||||
set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_DATA_SEL_0 {0}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.CPLL_FBDIV_0 {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLK25_DIV_0 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLK25_DIV_0 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_DATA_SEL_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.CPLL_FBDIV_1 {2}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CLK25_DIV_1 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.TX_CLK25_DIV_1 {10}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_pzslb_gt
|
||||
set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_pzslb_gt
|
||||
set axi_pz_xcvrlb [create_bd_cell -type ip -vlnv analog.com:user:axi_xcvrlb:1.0 axi_pz_xcvrlb]
|
||||
set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_pz_xcvrlb
|
||||
|
||||
set util_pzslb_gtlb_0 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_0]
|
||||
set util_pzslb_gtlb_1 [create_bd_cell -type ip -vlnv analog.com:user:util_gtlb:1.0 util_pzslb_gtlb_1]
|
||||
create_bd_port -dir I gt_ref_clk
|
||||
create_bd_port -dir I -from 1 -to 0 gt_rx_p
|
||||
create_bd_port -dir I -from 1 -to 0 gt_rx_n
|
||||
create_bd_port -dir O -from 1 -to 0 gt_tx_p
|
||||
create_bd_port -dir O -from 1 -to 0 gt_tx_n
|
||||
|
||||
ad_cpu_interconnect 0x44A60000 axi_pzslb_gt
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_pzslb_gt/m_axi
|
||||
|
||||
create_bd_port -dir I gt_ref_clk_0
|
||||
create_bd_port -dir I gt_ref_clk_1
|
||||
create_bd_port -dir I gt_rx_0_p
|
||||
create_bd_port -dir I gt_rx_0_n
|
||||
create_bd_port -dir O gt_tx_0_p
|
||||
create_bd_port -dir O gt_tx_0_n
|
||||
create_bd_port -dir I gt_rx_1_p
|
||||
create_bd_port -dir I gt_rx_1_n
|
||||
create_bd_port -dir O gt_tx_1_p
|
||||
create_bd_port -dir O gt_tx_1_n
|
||||
|
||||
ad_connect sys_cpu_clk util_pzslb_gtlb_0/up_clk
|
||||
ad_connect sys_cpu_resetn util_pzslb_gtlb_0/up_rstn
|
||||
ad_connect util_pzslb_gtlb_0/qpll_ref_clk gt_ref_clk_0
|
||||
ad_connect util_pzslb_gtlb_0/cpll_ref_clk gt_ref_clk_0
|
||||
ad_connect util_pzslb_gtlb_0/rx_p gt_rx_0_p
|
||||
ad_connect util_pzslb_gtlb_0/rx_n gt_rx_0_n
|
||||
ad_connect util_pzslb_gtlb_0/tx_p gt_tx_0_p
|
||||
ad_connect util_pzslb_gtlb_0/tx_n gt_tx_0_n
|
||||
ad_connect sys_cpu_clk util_pzslb_gtlb_1/up_clk
|
||||
ad_connect sys_cpu_resetn util_pzslb_gtlb_1/up_rstn
|
||||
ad_connect util_pzslb_gtlb_1/qpll_ref_clk gt_ref_clk_0
|
||||
ad_connect util_pzslb_gtlb_1/cpll_ref_clk gt_ref_clk_0
|
||||
ad_connect util_pzslb_gtlb_1/rx_p gt_rx_1_p
|
||||
ad_connect util_pzslb_gtlb_1/rx_n gt_rx_1_n
|
||||
ad_connect util_pzslb_gtlb_1/tx_p gt_tx_1_p
|
||||
ad_connect util_pzslb_gtlb_1/tx_n gt_tx_1_n
|
||||
ad_connect axi_pzslb_gt/gt_qpll_0 util_pzslb_gtlb_0/gt_qpll_0
|
||||
ad_connect axi_pzslb_gt/gt_pll_0 util_pzslb_gtlb_0/gt_pll_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_0 util_pzslb_gtlb_0/gt_rx_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_0 util_pzslb_gtlb_0/gt_tx_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_ip_0 util_pzslb_gtlb_0/gt_rx_ip_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_ip_0 util_pzslb_gtlb_0/gt_tx_ip_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_0 util_pzslb_gtlb_0/rx_gt_comma_align_enb_0
|
||||
ad_connect axi_pzslb_gt/gt_pll_1 util_pzslb_gtlb_1/gt_pll_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_1 util_pzslb_gtlb_1/gt_rx_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_1 util_pzslb_gtlb_1/gt_tx_0
|
||||
ad_connect axi_pzslb_gt/gt_rx_ip_1 util_pzslb_gtlb_1/gt_rx_ip_0
|
||||
ad_connect axi_pzslb_gt/gt_tx_ip_1 util_pzslb_gtlb_1/gt_tx_ip_0
|
||||
ad_connect axi_pzslb_gt/rx_gt_comma_align_enb_1 util_pzslb_gtlb_1/rx_gt_comma_align_enb_0
|
||||
ad_cpu_interconnect 0x44A60000 axi_pz_xcvrlb
|
||||
ad_connect axi_pz_xcvrlb/ref_clk gt_ref_clk
|
||||
ad_connect axi_pz_xcvrlb/rx_p gt_rx_p
|
||||
ad_connect axi_pz_xcvrlb/rx_n gt_rx_n
|
||||
ad_connect axi_pz_xcvrlb/tx_p gt_tx_p
|
||||
ad_connect axi_pz_xcvrlb/tx_n gt_tx_n
|
||||
|
||||
# un-used io (regular)
|
||||
|
||||
set axi_gpreg [create_bd_cell -type ip -vlnv analog.com:user:axi_gpreg:1.0 axi_gpreg]
|
||||
set_property -dict [list CONFIG.NUM_OF_CLK_MONS {8}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.NUM_OF_CLK_MONS {3}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_0 {1}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_1 {1}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_2 {1}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_3 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_4 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_5 {1}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_6 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.BUF_ENABLE_7 {0}] $axi_gpreg
|
||||
set_property -dict [list CONFIG.NUM_OF_IO {4}] $axi_gpreg
|
||||
|
||||
ad_cpu_interconnect 0x41200000 axi_gpreg
|
||||
|
||||
create_bd_port -dir I clk_0
|
||||
create_bd_port -dir I clk_1
|
||||
ad_connect clk_0 axi_gpreg/d_clk_0
|
||||
ad_connect clk_1 axi_gpreg/d_clk_1
|
||||
ad_connect gt_ref_clk_0 axi_gpreg/d_clk_2
|
||||
ad_connect util_pzslb_gtlb_0/rx_clk axi_gpreg/d_clk_3
|
||||
ad_connect util_pzslb_gtlb_0/tx_clk axi_gpreg/d_clk_4
|
||||
ad_connect gt_ref_clk_1 axi_gpreg/d_clk_5
|
||||
ad_connect util_pzslb_gtlb_1/rx_clk axi_gpreg/d_clk_6
|
||||
ad_connect util_pzslb_gtlb_1/tx_clk axi_gpreg/d_clk_7
|
||||
|
||||
create_bd_port -dir I -from 31 -to 0 gp_in_0
|
||||
create_bd_port -dir I -from 31 -to 0 gp_in_1
|
||||
create_bd_port -dir I -from 31 -to 0 gp_in_2
|
||||
create_bd_port -dir I -from 31 -to 0 gp_in_3
|
||||
create_bd_port -dir O -from 31 -to 0 gp_out_0
|
||||
create_bd_port -dir O -from 31 -to 0 gp_out_1
|
||||
create_bd_port -dir O -from 31 -to 0 gp_out_2
|
||||
create_bd_port -dir O -from 31 -to 0 gp_out_3
|
||||
create_bd_port -dir O -from 31 -to 0 gp_ioenb_0
|
||||
create_bd_port -dir O -from 31 -to 0 gp_ioenb_1
|
||||
create_bd_port -dir O -from 31 -to 0 gp_ioenb_2
|
||||
create_bd_port -dir O -from 31 -to 0 gp_ioenb_3
|
||||
create_bd_port -dir I clk_0
|
||||
create_bd_port -dir I clk_1
|
||||
create_bd_port -dir I clk_2
|
||||
|
||||
ad_connect clk_0 axi_gpreg/d_clk_0
|
||||
ad_connect clk_1 axi_gpreg/d_clk_1
|
||||
ad_connect clk_2 axi_gpreg/d_clk_2
|
||||
ad_connect gp_in_0 axi_gpreg/up_gp_in_0
|
||||
ad_connect gp_in_1 axi_gpreg/up_gp_in_1
|
||||
ad_connect gp_in_2 axi_gpreg/up_gp_in_2
|
||||
ad_connect gp_in_3 axi_gpreg/up_gp_in_3
|
||||
ad_connect gp_out_0 axi_gpreg/up_gp_out_0
|
||||
ad_connect gp_out_1 axi_gpreg/up_gp_out_1
|
||||
ad_connect gp_out_2 axi_gpreg/up_gp_out_2
|
||||
ad_connect gp_out_3 axi_gpreg/up_gp_out_3
|
||||
ad_connect gp_ioenb_0 axi_gpreg/up_gp_ioenb_0
|
||||
ad_connect gp_ioenb_1 axi_gpreg/up_gp_ioenb_1
|
||||
ad_connect axi_gpreg/up_gp_in_2 util_pzslb_gtlb_0/up_gp_out
|
||||
ad_connect axi_gpreg/up_gp_out_2 util_pzslb_gtlb_0/up_gp_in
|
||||
ad_connect axi_gpreg/up_gp_in_3 util_pzslb_gtlb_1/up_gp_out
|
||||
ad_connect axi_gpreg/up_gp_out_3 util_pzslb_gtlb_1/up_gp_in
|
||||
ad_connect gp_ioenb_2 axi_gpreg/up_gp_ioenb_2
|
||||
ad_connect gp_ioenb_3 axi_gpreg/up_gp_ioenb_3
|
||||
ad_cpu_interconnect 0x41200000 axi_gpreg
|
||||
|
||||
## temporary (remove ila indirectly)
|
||||
|
||||
delete_bd_objs [get_bd_cells ila_adc]
|
||||
delete_bd_objs [get_bd_nets axi_ad9361_tdd_dbg] [get_bd_cells ila_tdd]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue