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axi_dmac: Fix issues with non 64-bit AXI masters 

Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2014-04-08 17:22:17 +02:00
parent 36ef882da0
commit dc7b3e085c
8 changed files with 73 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
library/axi_dmac/2d_transfer.v
View File

@ -43,8 +43,8 @@ module dmac_2d_transfer (
input req_valid,
output reg req_ready,
input [31:C_ADDR_ALIGN_BITS] req_dest_address,
input [31:C_ADDR_ALIGN_BITS] req_src_address,
input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_x_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_y_length,
input [C_DMA_LENGTH_WIDTH-1:0] req_dest_stride,
@ -54,18 +54,19 @@ module dmac_2d_transfer (
output reg out_req_valid,
input out_req_ready,
output [31:C_ADDR_ALIGN_BITS] out_req_dest_address,
output [31:C_ADDR_ALIGN_BITS] out_req_src_address,
output [31:C_BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
output [31:C_BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
output [C_DMA_LENGTH_WIDTH-1:0] out_req_length,
output reg out_req_sync_transfer_start,
input out_eot
);
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH_SRC = 3;
parameter C_BYTES_PER_BEAT_WIDTH_DEST = 3;
reg [31:C_ADDR_ALIGN_BITS] dest_address;
reg [31:C_ADDR_ALIGN_BITS] src_address;
reg [31:C_BYTES_PER_BEAT_WIDTH_DEST] dest_address;
reg [31:C_BYTES_PER_BEAT_WIDTH_SRC] src_address;
reg [C_DMA_LENGTH_WIDTH-1:0] x_length;
reg [C_DMA_LENGTH_WIDTH-1:0] y_length;
reg [C_DMA_LENGTH_WIDTH-1:0] dest_stride;
@ -125,8 +126,8 @@ begin
end
end else begin
if (out_req_valid && out_req_ready) begin
dest_address <= dest_address + dest_stride[C_DMA_LENGTH_WIDTH-1:C_ADDR_ALIGN_BITS];
src_address <= src_address + src_stride[C_DMA_LENGTH_WIDTH-1:C_ADDR_ALIGN_BITS];
dest_address <= dest_address + dest_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[C_DMA_LENGTH_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
if (y_length == 0) begin

12
library/axi_dmac/address_generator.v
View File

@ -41,7 +41,7 @@ module dmac_address_generator (
input req_valid,
output reg req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output reg [C_ID_WIDTH-1:0] id,
@ -64,11 +64,11 @@ module dmac_address_generator (
output [ 3:0] cache
);
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_ID_WIDTH = 3;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8);
localparam MAX_BEATS_PER_BURST = 2**(C_BEATS_PER_BURST_WIDTH);
`include "inc_id.h"
@ -80,9 +80,9 @@ assign len = length;
assign size = $clog2(C_DMA_DATA_WIDTH/8);
reg [7:0] length = 'h0;
reg [31-C_ADDR_ALIGN_BITS:0] address = 'h00;
reg [31-C_BYTES_PER_BEAT_WIDTH:0] address = 'h00;
reg [C_BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00;
assign addr = {address, {C_ADDR_ALIGN_BITS{1'b0}}};
assign addr = {address, {C_BYTES_PER_BEAT_WIDTH{1'b0}}};
// If we already asserted addr_valid we have to wait until it is accepted before
// we can disable the address generator.

42
library/axi_dmac/axi_dmac.v
View File

@ -140,7 +140,6 @@ parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_2D_TRANSFER = 1;
@ -166,11 +165,28 @@ localparam DMA_TYPE_AXI_STREAM = 1;
localparam DMA_TYPE_FIFO = 2;
localparam PCORE_VERSION = 'h00040061;
localparam DMA_ADDR_WIDTH = 32 - C_ADDR_ALIGN_BITS;
localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM;
localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
localparam BYTES_PER_BEAT_WIDTH_DEST = C_DMA_DATA_WIDTH_DEST > 1024 ? 8 :
C_DMA_DATA_WIDTH_DEST > 512 ? 7 :
C_DMA_DATA_WIDTH_DEST > 256 ? 6 :
C_DMA_DATA_WIDTH_DEST > 128 ? 5 :
C_DMA_DATA_WIDTH_DEST > 64 ? 4 :
C_DMA_DATA_WIDTH_DEST > 32 ? 3 :
C_DMA_DATA_WIDTH_DEST > 16 ? 2 :
C_DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_SRC = C_DMA_DATA_WIDTH_SRC > 1024 ? 8 :
C_DMA_DATA_WIDTH_SRC > 512 ? 7 :
C_DMA_DATA_WIDTH_SRC > 256 ? 6 :
C_DMA_DATA_WIDTH_SRC > 128 ? 5 :
C_DMA_DATA_WIDTH_SRC > 64 ? 4 :
C_DMA_DATA_WIDTH_SRC > 32 ? 3 :
C_DMA_DATA_WIDTH_SRC > 16 ? 2 :
C_DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
// Register interface signals
reg [31:0] up_rdata = 'd0;
reg up_ack = 1'b0;
@ -206,8 +222,8 @@ reg [1:0] up_transfer_id;
reg [1:0] up_transfer_id_eot;
reg [3:0] up_transfer_done_bitmap;
reg [31:C_ADDR_ALIGN_BITS] up_dma_dest_address = 'h00;
reg [31:C_ADDR_ALIGN_BITS] up_dma_src_address = 'h00;
reg [31:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00;
reg [31:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_x_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00;
reg [C_DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00;
@ -315,8 +331,8 @@ begin
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
12'h103: if (C_CYCLIC) up_dma_cyclic <= up_wdata[0];
12'h104: up_dma_dest_address <= up_wdata[31:C_ADDR_ALIGN_BITS];
12'h105: up_dma_src_address <= up_wdata[31:C_ADDR_ALIGN_BITS];
12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
12'h106: up_dma_x_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h107: up_dma_y_length <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
12'h108: up_dma_dest_stride <= up_wdata[C_DMA_LENGTH_WIDTH-1:0];
@ -342,8 +358,8 @@ begin
12'h101: up_rdata <= up_transfer_id;
12'h102: up_rdata <= up_dma_req_valid;
12'h103: up_rdata <= {31'h00, up_dma_cyclic}; // Flags
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{C_ADDR_ALIGN_BITS{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{C_ADDR_ALIGN_BITS{1'b0}}} : 'h00;
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
12'h107: up_rdata <= C_2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= C_2D_TRANSFER ? up_dma_dest_stride : 'h00;
@ -382,8 +398,8 @@ end
wire dma_req_valid;
wire dma_req_ready;
wire [31:C_ADDR_ALIGN_BITS] dma_req_dest_address;
wire [31:C_ADDR_ALIGN_BITS] dma_req_src_address;
wire [31:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address;
wire [31:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address;
wire [C_DMA_LENGTH_WIDTH-1:0] dma_req_length;
wire dma_req_eot;
wire dma_req_sync_transfer_start;
@ -397,7 +413,8 @@ generate if (C_2D_TRANSFER == 1) begin
dmac_2d_transfer #(
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS)
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
) i_2d_transfer (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
@ -439,7 +456,8 @@ dmac_request_arb #(
.C_DMA_DATA_WIDTH_SRC(C_DMA_DATA_WIDTH_SRC),
.C_DMA_DATA_WIDTH_DEST(C_DMA_DATA_WIDTH_DEST),
.C_DMA_LENGTH_WIDTH(C_DMA_LENGTH_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.C_BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.C_DMA_TYPE_DEST(C_DMA_TYPE_DEST),
.C_DMA_TYPE_SRC(C_DMA_TYPE_SRC),
.C_CLKS_ASYNC_REQ_SRC(C_CLKS_ASYNC_REQ_SRC),

2
library/axi_dmac/axi_dmac_alt.v
View File

@ -189,7 +189,6 @@ module axi_dmac_alt (
parameter PCORE_ID = 0;
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_DMA_LENGTH_WIDTH = 14;
parameter C_2D_TRANSFER = 1;
parameter C_CLKS_ASYNC_REQ_SRC = 1;
@ -361,7 +360,6 @@ module axi_dmac_alt (
.C_HIGHADDR (32'hffffffff),
.C_DMA_DATA_WIDTH_SRC (C_DMA_DATA_WIDTH_SRC),
.C_DMA_DATA_WIDTH_DEST (C_DMA_DATA_WIDTH_DEST),
.C_ADDR_ALIGN_BITS (C_ADDR_ALIGN_BITS),
.C_DMA_LENGTH_WIDTH (C_DMA_LENGTH_WIDTH),
.C_2D_TRANSFER (C_2D_TRANSFER),
.C_CLKS_ASYNC_REQ_SRC (C_CLKS_ASYNC_REQ_SRC),

9
library/axi_dmac/dest_axi_mm.v
View File

@ -42,7 +42,7 @@ module dmac_dest_mm_axi (
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [C_BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
@ -95,9 +95,8 @@ module dmac_dest_mm_axi (
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH = $clog2(C_DMA_DATA_WIDTH/8);
parameter C_BEATS_PER_BURST_WIDTH = 4;
parameter C_BYTES_PER_BEAT_WIDTH = 3;
reg [(C_DMA_DATA_WIDTH/8)-1:0] wstrb;
@ -132,8 +131,8 @@ splitter #(
dmac_address_generator #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
@ -198,7 +197,7 @@ begin
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= 8'b11111111;
wstrb <= {(C_DMA_DATA_WIDTH/8){1'b1}};
end
end

40
library/axi_dmac/request_arb.v
View File

@ -42,8 +42,8 @@ module dmac_request_arb (
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_dest_address,
input [31:C_ADDR_ALIGN_BITS] req_src_address,
input [31:C_BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:C_BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [C_DMA_LENGTH_WIDTH-1:0] req_length,
input req_sync_transfer_start,
@ -137,7 +137,9 @@ module dmac_request_arb (
parameter C_DMA_DATA_WIDTH_SRC = 64;
parameter C_DMA_DATA_WIDTH_DEST = 64;
parameter C_DMA_LENGTH_WIDTH = 24;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH_DEST = $clog2(C_DMA_DATA_WIDTH_DEST/8);
parameter C_BYTES_PER_BEAT_WIDTH_SRC = $clog2(C_DMA_DATA_WIDTH_SRC/8);
parameter C_DMA_TYPE_DEST = DMA_TYPE_MM_AXI;
parameter C_DMA_TYPE_SRC = DMA_TYPE_FIFO;
@ -158,7 +160,8 @@ localparam DMA_TYPE_MM_AXI = 0;
localparam DMA_TYPE_STREAM_AXI = 1;
localparam DMA_TYPE_FIFO = 2;
localparam DMA_ADDR_WIDTH = 32 - C_ADDR_ALIGN_BITS;
localparam DMA_ADDR_WIDTH_DEST = 32 - C_BYTES_PER_BEAT_WIDTH_DEST;
localparam DMA_ADDR_WIDTH_SRC = 32 - C_BYTES_PER_BEAT_WIDTH_SRC;
localparam DMA_DATA_WIDTH = C_DMA_DATA_WIDTH_SRC < C_DMA_DATA_WIDTH_DEST ?
C_DMA_DATA_WIDTH_DEST : C_DMA_DATA_WIDTH_SRC;
@ -169,10 +172,8 @@ localparam DMA_DATA_WIDTH = C_DMA_DATA_WIDTH_SRC < C_DMA_DATA_WIDTH_DEST ?
// differ, so beats per burst may also differ
parameter BYTES_PER_BURST_WIDTH = $clog2(C_MAX_BYTES_PER_BURST);
parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(C_DMA_DATA_WIDTH_SRC/8);
parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(C_DMA_DATA_WIDTH_DEST/8);
localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC;
localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST;
localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_SRC;
localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - C_BYTES_PER_BEAT_WIDTH_DEST;
localparam BURSTS_PER_TRANSFER_WIDTH = C_DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH;
@ -211,9 +212,9 @@ wire dest_clk;
wire dest_resetn;
wire dest_req_valid;
wire dest_req_ready;
wire [DMA_ADDR_WIDTH-1:0] dest_req_address;
wire [DMA_ADDR_WIDTH_DEST-1:0] dest_req_address;
wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_req_last_burst_length;
wire [BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
wire [C_BYTES_PER_BEAT_WIDTH_DEST-1:0] dest_req_last_beat_bytes;
wire dest_response_valid;
wire dest_response_ready;
@ -238,7 +239,7 @@ wire src_clk;
wire src_resetn;
wire src_req_valid;
wire src_req_ready;
wire [DMA_ADDR_WIDTH-1:0] src_req_address;
wire [DMA_ADDR_WIDTH_SRC-1:0] src_req_address;
wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length;
wire src_req_sync_transfer_start;
@ -378,9 +379,8 @@ assign dbg_dest_data_id = dest_data_id;
dmac_dest_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST),
.C_BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST)
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_DEST)
) i_dest_dma_mm (
.m_axi_aclk(m_dest_axi_aclk),
.m_axi_aresetn(m_dest_axi_aresetn),
@ -586,8 +586,8 @@ assign dbg_src_data_id = src_data_id;
dmac_src_mm_axi #(
.C_ID_WIDTH(C_ID_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH_SRC),
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC)
.C_BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH_SRC)
) i_src_dma_mm (
.m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(m_src_axi_aresetn),
@ -901,7 +901,7 @@ splitter #(
);
axi_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH + BEATS_PER_BURST_WIDTH_DEST + BYTES_PER_BEAT_WIDTH_DEST),
.C_DATA_WIDTH(DMA_ADDR_WIDTH_DEST + BEATS_PER_BURST_WIDTH_DEST + C_BYTES_PER_BEAT_WIDTH_DEST),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_DEST_REQ)
) i_dest_req_fifo (
@ -912,8 +912,8 @@ axi_fifo #(
.s_axis_empty(req_dest_empty),
.s_axis_data({
req_dest_address,
req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST],
req_length[BYTES_PER_BEAT_WIDTH_DEST-1:0]
req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_DEST],
req_length[C_BYTES_PER_BEAT_WIDTH_DEST-1:0]
}),
.m_axis_aclk(dest_clk),
.m_axis_aresetn(dest_resetn),
@ -927,7 +927,7 @@ axi_fifo #(
);
axi_fifo #(
.C_DATA_WIDTH(DMA_ADDR_WIDTH + BEATS_PER_BURST_WIDTH_SRC + 1),
.C_DATA_WIDTH(DMA_ADDR_WIDTH_SRC + BEATS_PER_BURST_WIDTH_SRC + 1),
.C_ADDRESS_WIDTH(0),
.C_CLKS_ASYNC(C_CLKS_ASYNC_REQ_SRC)
) i_src_req_fifo (
@ -938,7 +938,7 @@ axi_fifo #(
.s_axis_empty(req_src_empty),
.s_axis_data({
req_src_address,
req_length[BYTES_PER_BURST_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC],
req_length[BYTES_PER_BURST_WIDTH-1:C_BYTES_PER_BEAT_WIDTH_SRC],
req_sync_transfer_start
}),
.m_axis_aclk(src_clk),

6
library/axi_dmac/src_axi_mm.v
View File

@ -42,7 +42,7 @@ module dmac_src_mm_axi (
input req_valid,
output req_ready,
input [31:C_ADDR_ALIGN_BITS] req_address,
input [31:C_BYTES_PER_BEAT_WIDTH] req_address,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input enable,
@ -86,7 +86,7 @@ module dmac_src_mm_axi (
parameter C_ID_WIDTH = 3;
parameter C_DMA_DATA_WIDTH = 64;
parameter C_ADDR_ALIGN_BITS = 3;
parameter C_BYTES_PER_BEAT_WIDTH = 3;
parameter C_BEATS_PER_BURST_WIDTH = 4;
`include "resp.h"
@ -122,9 +122,9 @@ splitter #(
);
dmac_address_generator #(
.C_ADDR_ALIGN_BITS(C_ADDR_ALIGN_BITS),
.C_ID_WIDTH(C_ID_WIDTH),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH),
.C_BYTES_PER_BEAT_WIDTH(C_BYTES_PER_BEAT_WIDTH),
.C_DMA_DATA_WIDTH(C_DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),

2
projects/fmcomms1/common/fmcomms1_bd.tcl
View File

@ -32,7 +32,6 @@
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma
if {$sys_zynq == 1} {
@ -61,7 +60,6 @@ if {$sys_zynq == 1} {
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_ADDR_ALIGN_BITS {3}] $axi_ad9643_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma
if {$sys_zynq == 1} {